Globalfoundries U.S. Inc.

Chandrahasa Reddy Dinnipati

Ramesh Raghavan

Bipul C Paul

Balaji Jayaraman

Toshiaki Kirihata

Philipp Bernhard Mosch

Embodiments of the disclosure provide a memory assembly with body biasing and related methods to operate such a structure. A structure according to the disclosure includes a memory cell having a pair of memory transistors each having a gate coupled to a word line. A pair of diode-connected transistors each have a source/drain (S/D) terminal coupled to a respective S/D terminal of one of the pair of memory transistors through a multiplexer. A bias voltage source is coupled to each body of the pair of diode-connected transistors or each body of the pair of memory transistors. The bias voltage source applies a different bias voltage to each body of the pair of diode-connected transistors or each body of the pair of memory transistors.

Memory assembly with body biasing and related methods

Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

Sense circuit and high-speed memory structure incorporating the sense circuit

Embodiments of the present disclosure provide an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier.

Apparatus and related method to indicate stability and instability in bit cell

A structure includes an array of nonvolatile memory cells, wordlines and bitlines connected to the nonvolatile memory cells, sense amplifiers connected to the nonvolatile memory cells, and reference cells connected to the sense amplifiers. Each of the reference cells has a transistor connected to a variable resistor, one of the wordlines, a reference bitline separate from the bitlines, and the sense amplifiers.

Resistive memory array with localized reference cells

A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

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Andhra Pradesh, India

Chandrahasa Reddy Dinnipati