Cisco Technology, Inc.

Nebbiolo Technologies, Inc.

Silicon Graphics, Incorporated

Other

Mips Technologies, Inc.

Silicon Graphics Computer Systems, Inc.

Chandra Shekhar Joshi

Jay Sethuram

Richard Joseph Weber

Paul Kingsley Rodman

Peter Y Hsu

Srinivasa Rao Malladi

Rajiv Dattatraya Kane

Amir Nayyarhabibi

Monica R Nofal

Flavio Giovanni Bonomi

Kannan Devarajan

Pankaj Bhagra

Palani Chinnakannan

Joseph P Bratt

William A Huffman

Joseph T Scanlon

John Brennan

Man K Tang

Adaptive scheduling of compute functions in a fog network is described herein. An example method includes synchronizing kernel and hypervisor scheduling of applications used to control one or more edge devices using a global schedule, wherein the global schedule comprises timeslots for applications, and adapting the timeslots in real-time or near real-time based on application-based time related feedback that is indicative of time delays.

Adaptive scheduling for edge devices and networks

Disclosed herein are enhancements for operating an input/output (I/O) management cluster with end I/O devices. In one implementation, a method of operating an I/O cluster includes, in a first I/O management node of the I/O management cluster, executing a first application to manage data for an I/O device communicatively coupled via at least one switch to the first I/O management node. The method further provides identifying a failure in the first I/O management node related to processing the data for the I/O device and, in response to the failure, configuring the at least one switch to communicate the data for the I/O device with a second I/O management node of the I/O management cluster. The method also includes, in the second I/O management node and after configuring the at least one switch, executing a second application to manage the data for the I/O device.

High availability input/output management nodes

Provided herein are exemplary systems and methods for a fog computing facilitated flexible factory including establishing a physical production process as part of a work cell, establishing a sensing process as part of the work cell for the physical production process, establishing a monitoring process for the sensing process and the physical production process, establishing a managing process for the monitoring process, the sensing process and the physical production process, establishing a planning process for the managing process, the monitoring process, the sensing process and the physical production process, and establishing a fog node as part of the work cell for all of the processes.

Fog computing facilitated flexible factory

A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network is provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A provisioning register stores provisioning information describing the communication system and the communication ports. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally its intermediate states are restored, processed, and saved when it changes to process a different data stream or a different frame of data of a given service. An elastic storage means allows the SONET/SDH byte engine and the service byte engine to operate independent of one another in an asynchronous mode.

Method and apparatus for transceiving multiple services data simultaneously over SONET/SDH

A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network is provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A provisioning register stores provisioning information describing the communication system and the communication ports. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally its intermediate states are restored, processed, and saved when it changes to process a different data stream or a different frame of data of a given service. An elastic storage means allows the SONET/SDH byte engine and the service byte engine to operate independent of one another in an asynchronous mode.

A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network are provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally intermediate states are restored, processed, and saved when the service byte engine changes to process a different data stream or a different frame of data of a given service.

Multi-PHY addressing from source to destination in which n-number of channels or ports are used in a PHY layer device for communication with a link layer device. A single link layer to a single-PHY layer topology and a single link layer to a multi-PHY layer topology comprising multiple ports or channels receives a plurality of channels groups. Status indication signal is provided on continuous basis for the direct status for up to a predetermined number of channels.

Method and system for multi-PHY addressing

A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit. A feedback path is also provided to reload an instruction not previously dispatched.

Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution

A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions

A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

Invalidating instructions in fetched instruction blocks upon predicted

A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.

Apparatus for processing instructions in a computing system

A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to 'switch to debug mode,' the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

Growing community of inventors

Saratoga, CA, United States of America

Chandra Shekhar Joshi