Micron Technology Incorporated

Chandra S Danana

Stephen W Russell

Zia Alan Shafi

Luca Laurin

Ahmed Nayaz Noemaun

Durga Prasanna Panda

Sara Vigano

Michael J Irwin

Rekha Chithra Thomas

Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.

Memory device decoder configurations

Growing community of inventors

Boise, ID, United States of America

Chandra S Danana