Nxp B.v.

National Semiconductor Corporation

Nxp Usa, Inc.

Chandra Prakash Tiwari

Siamak Delshadpour

Hendrik Boezen

Ravi Kumar

Tao Sun

Michael Joehren

Henricus Cornelis Johannes Büthker

Abhijeet Chandrakant Kulkarni

Ranjeet Kumar Gupta

Anand Shirwal

Yehao Shen

Hongyue Zhu

Peiying Song

An electronic circuit that switchably generates an offset-bias output at a offset-bias voltage in response to at least an enable signal at a low voltage relative to the offset-bias voltage is provided. The electronic circuit includes a reference input terminal, configured to be connected to a reference voltage; a low-voltage-input terminal, configured to receive the enable signal at a first voltage; a high-voltage-supply terminal, configured to receive power at a second voltage; an offset-bias output terminal, configured to output the offset-bias output, the offset-bias voltage being less than the second voltage; a voltage-offset circuit configured to generate the offset-bias voltage from the second voltage; a bias circuit configured to switchably provide a bias current to the voltage-offset circuit; and a high-voltage stand-off circuit, connected between the bias circuit and the voltage-offset circuit and configured to withstand a voltage difference between the second voltage and the reference voltage.

Level shifter and multi-voltage-domain circuits

Embodiments of bidirectional repeaters and communications systems are disclosed. In an embodiment, a bidirectional repeater includes a digital state machine configured to control the bidirectional repeater to operate under a functional mode or under a bypass mode and a bypass mode driver configured to automatically detect a direction of signal through input/output (I/O) terminals of the bidirectional repeater and to allow a signal to pass through the bidirectional repeater based on the direction of signal under the bypass mode.

Bidirectional bypass mode

A driver circuit of a voltage translator includes a bias voltage generator, a drive voltage generator, an output voltage generator, and a filter circuit. The bias voltage generator is configured to receive a supply voltage, a first input voltage, and a feedback voltage, and generate a bias voltage. The feedback voltage controls an amplitude of the bias voltage. The drive voltage generator is configured to receive the supply voltage, the first input voltage, and the bias voltage, and generate a drive voltage. The output voltage generator is configured to receive the supply voltage, a second input voltage, and the drive voltage, and generate an output voltage. The drive voltage controls a slew rate of the output voltage. The filter circuit is configured to receive the output voltage, and generates and provides the feedback voltage to the bias voltage generator.

Driver circuit of voltage translator

A voltage translator having first and second one-shots shifts a voltage level of a first voltage signal to generate a second voltage signal, and vice-versa. The first one-shot generates a first driver signal when the first voltage signal goes from low to high based on a time duration for which the first voltage signal remains high. The second voltage signal is generated based on the first driver signal. Similarly, the second one-shot generates the first voltage signal when the second voltage signal goes from a low to high based on a time duration for which the second voltage signal remains high.

Bidirectional voltage translator with pulse width control

A bi-directional level translator with fast rise and fall times and low current leakage is suitable for use with devices connected using a SPMI bus. The level translator passes signals between first and second voltage domains that operate at different voltage levels. The level translator has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is located between the first voltage source and the first terminal and a second switch is located between the second voltage source and the second terminal. The first and second switches are operable to reduce current leakage of the level translator.

Level translator for SPMI bus

A bidirectional voltage translator shifts a voltage level of a first voltage signal to generate a second voltage signal, and vice-versa. The voltage translator includes first and second I/O terminals for receiving and outputting the first and second voltage signals, respectively, and first and second one-shot circuits connected to first and second output transistors, respectively. The outputs of the transistors are connected to the first and second I/O terminals, respectively, and also are fed back to the respective one-shot circuits. When the output of the voltage translator has a high slew-rate, the one of the first and second one-shot circuits that corresponds to the output modulates the gate voltage of the corresponding output transistor based on the feedback signal to control the slew-rate of the output.

Voltage translator with output slew rate control

For an LED lighting application, overshoot-protection circuitry prevents an LED controller, such as a matrix lighting controller (MLC) that controls an array of LEDs, from falsely detecting an open-circuit condition in an LED controlled by the LED controller, by limiting the magnitude of an overshoot voltage (due to long-wire parasitic inductances) from occurring when a switch in the LED controller that is used to control the LED is turned off.

Overshoot protection circuit for LED lighting

A voltage regulator formed on an integrated circuit is provided that includes a single voltage source and a bias voltage generator. The single voltage source comprises a reference voltage source that is operable to provide a reference voltage. The bias voltage generator is coupled to the reference voltage source and is operable to generate a bias voltage based on the reference voltage.

Voltage regulator using a single voltage source and method

A charge sharing suppression circuit for a charge pump circuit in a phase locked loop is disclosed that is capable of suppressing charge sharing due to static phase error in the phase locked loop. A return path is provided to allow charge pump currents to flow when static phase error exists. A first switch in the return path closes in response to an UP signal from a phase frequency detector and a second switch closes in response to an inverted version of a DN signal. A third switch in the return path closes in response to an inverted version of an UP signal and a fourth switch closes in response to a DN signal. The return path is disabled in the absence of static phase error.

Growing community of inventors

Bengaluru, India

Chandra Prakash Tiwari