Mips Technologies, Inc.

Altera Corporation

Arm Finance Overseas Limited

Chandlee B Harrell

Radhika Thekkath

G Michael Uhler

Ying-wai Ho

Adityo Prakash

Edward R Ratner

Thomas D Miller

Hon Hing So

A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.

Processor having a compare extension of an instruction set architecture

A method and apparatus for client-side detection of network congestion in a best-effort packet network comprising streaming media traffic is disclosed. Said method and apparatus provide for quality streaming media services in a congested network with constrained bandwidth over the last-mile link. A client media buffer detects at least one level of congestion and signals a server to enact at least one error mechanism. Preferred error mechanisms include packet retransmissions, stream prioritization, stream acceleration, changes in media compression rate, and changes in media resolution. Said method and apparatus allow distributed management of network congestion for networks comprising multiple clients and carrying significant streaming media traffic.

Flow control method for quality streaming of audio/video/media over packet networks

A processor having a conditional branch extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to branching if, for example, either one of two condition codes is false or true, if any of three condition codes are false or true, or if any one of four condition codes are false or true.

Processor having a conditional branch extension of an instruction set architecture

A processor having an arithmetic extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to reduction add, reduction multiply, reciprocal, and reciprocal square root.

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Cupertino, CA, United States of America

Chandlee B Harrell