Arm Limited

Chander Sudanthi

Stuart David Biles

Nigel C Paver

Timothy Charles Mace

A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.

Data processor with hardware accelerator, accelerator interface and shared memory management unit

A processing systemincluding a memoryand a cache memoryis provided with a page status unitfor providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.

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Austin, TX, United States of America

Chander Sudanthi