Advanced Micro Devices Corporation

Intel Corporation

Chandan Egbert

Bahadir Erimli

Thomas J Runaldue

Amin Firoozshahian

Mrudula Kanuri

Denise Kerstein

Mahesh Srinivasa Maddury

Omid Azizi

Shashank C Merchant

John Mingyung Chiang

Andreas Kleen

Mahesh Madhav

Xiaohua Zhuang

Robert Alan Williams

Ian S Crayford

Ching Yu

Peter Ka-Fai Chow

Ian Lam

Eric Tsin-Ho Leung

Edward Yang

Vallath Nandakumar

Somnath Viswanath

Gopal S Krishna

Alexandre Y Solomatnikov

Eric Gouldey

David Hansen

Eric Tsin-ho Leung

John Peter Stevenson

Francesc Guim Bernat

Karthik Kumar

Thomas Willhalm

Ashok Raj

Ishwar Agarwal

Stephen R Van Doren

Vedaraman Geetha

Shr-Jie Tzeng

Marufa Kaniz

Philip Simmons

Henk G Neefs

Mustafa Hajeer

Mahesh Maddury

Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

Reservation architecture for overcommitted memory

Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

Hardware-assisted paging mechanisms

Examples relate to an approximative memory deduplication method, a controller apparatus or controller device for a memory or storage controller, a memory or storage controller, a computer system and to a computer program. The approximative memory deduplication method comprises determining a hash value of a data block. The hash value is based on a user-defined approximative hashing function. The approximative memory deduplication method comprises storing a quantized version of the data block based on the hash value using a memory or storage device of the computer system.

Concept for approximate deduplication in storage and memory

Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

Lazy memory deduplication

Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

Memory pressure notifier

A network switch includes network switch ports, each including a port filter configured for detecting user-selected attributes from a received layer 2 type data frame. Each port filter, upon detecting a user-selected attribute in a received layer 2 type data frame, sends a signal to a switching module indicating the determined presence of the user-selected attribute, enabling the switching module to generate a switching decision based on the corresponding user-selected attribute and based on a corresponding user-defined switching policy. The switching policy may specify a priority class, or a guaranteed quality of service (e.g., a guaranteed bandwidth), ensuring that the received layer 2 type data frame receives the appropriate switching support. The user-selected attributes for the port filter and the user-defined switching policy for the switching module are programmed by a host processor. Hence, the integrated network switch is able to perform advanced switching operations for layer 2 type data packets to ensure quality of service requirements, independent of priority information specified in the layer 2 type data packets, based on the user-selected attributes in the layer 2 type data packets and the user-defined switching policies established for the switching module.

Arrangement in a network switch for prioritizing data frames based on user-defined frame attributes

A network switch, configured for performing layerand layerswitching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a switching module for performing layerand layer(specifically Internet Protocol) switching operations, and a plurality of network switch ports, each configured for connecting the network switch to a corresponding subnetwork. The switching module includes address tables for storing address information (e.g., layerand layeraddress and switching information). The network switching module is configured for performing prescribed layerswitching that enables transfer of data packets between subnetworks, bypassing a router that normally would need to manage Internet protocol switching between subnetworks of the network. Hence, the network switch performs Internet Protocol switching for intranetwork (i.e., inter-subnetwork) traffic, improving efficiency of the router by enabling the router resources to support more subnetworks.

Layer 3 switching logic architecture in an integrated network switch

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

Apparatus and method for programmable memory access slot assignment

A network switch, configured for performing layerand layerswitching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a packet classifier module configured for generating a packet signature based on information within a received data packet and hash action values specified within a user-programmable template. In particular, the network switch stores a plurality of user-programmable templates, each configured for identifying a corresponding class of data packet. Each user-programmable template includes hash action values specifying initiation and termination of a hash function based on a byte offset of a received data packet. The packet classifier module includes a hash generator configured for generating hash values for selected bytes of the received data packet, and a template translator configured for controlling the hash generator for hashing the selected bytes of the received data packet based on the hash action values specified by a corresponding user-programmable template. Hence, a unique hash signature can be generated by supplying a data frame having a prescribed data values at the selected bytes of the user-programmable template; the hash signature can then be stored for comparison with incoming data packets during network switching operations. Hence, data packets can be classified at the wire rate by performing a hash-based search of selected bytes of the received data packet.

Packet classification using hash key signatures generated from interrupted hash function

A network switch includes a switching module and network switch ports connecting respective subnetworks. The switching module includes a plurality of address tables for storing address information (e.g., layer and layer address and switching information), where at least one table is configured for storing subnetwork identifiers of subnetworks that are reachable by the network switch.

Arrangement for switching data packets in a network switch based on subnet identifier

A network switch, configured for performing layer and layer switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a port filter configured for obtaining and filtering relevant layer and layer information from a received layer frame. Each port filter, upon filtering the relevant layer and layer information from a received layer frame, outputs the relevant layer and layer information to switching logic, enabling the switching logic to perform layer processing to determine a layer switching operation to be performed on the received layer frame. Hence, the switching logic performs the layer processing based on the relevant layer and layer information, without the necessity of parsing the received layer and layer information by the switching logic.

Arrangement for reducing layer 3 header data supplied to switching logic on a network switch

A switching system includes switches, each having a host processing unit and a switching unit, and a backbone link configured for transferring data packets between the switching units. One of the host processing units is configured as a master unit for generating a data frame having a destination address for a selected one of the switching units of a corresponding selected one of the other host processing units. The master unit outputs the data frame to the corresponding switching unit for transfer to the selected one switching unit via the backbone link. The selected one switching unit, in response to receiving the data frame having the corresponding destination address, forwards the data frame to the corresponding host processing unit for execution of a processing operation specified in the data frame. Hence, the switching system provides inter-processor communications using a preexisting backbone link, eliminating the necessity of a processor bus.

In-band management of a stacked group of switches by a single CPU

A network switch, configured for performing layer and layer switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a switching module having a shared address table storing address entries for both layer and layer address search operations for layer and layer processing. The shared address table is configured for storing in each address entry two key entries, and two pointer fields, enabling each address entry of the shared address table to logically belong to two separate and independent tables for search purposes.

Multiple key lookup arrangement for a shared switching logic address table in a network switch

A network switch configured for switching data packets across multiple ports uses decision making device to generate frame forwarding information. The decision making device employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The decision making device also includes a memory to store frame headers to minimize the signaling between the decision making device and the receive devices.

Multiport switch with plurality of logic engines for simultaneously processing different respective data frames

Growing community of inventors

San Jose, CA, United States of America

Chandan Egbert