Synopsys, Inc.

Chanaka Ranathunga

Ramesh Narayanaswamy

Subha S Chowdhury

Dinesh Madusanke Pasikku Hannadige

Subramanian Ganesan

Aditha Pabasara Rajakaruna

This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously with the first SVP and transmits data to the first SVP while simulating the first portion of the circuit design, wherein the first SVP uses the data while simulating the first portion of the circuit design.

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Kuliyapitiya, Sri Lanka

Chanaka Ranathunga