Skhynix Inc.

Chan Young Oh

Hoe Seung Jung

Heung Tae Jin

Na Ra Shin

A memory system includes: a memory device including first memory blocks, within which a single bit is to be programmed into a memory cell by using a single level cell (SLC) method, and second memory blocks, within which two or more bits are to be programmed into a memory cell by using a multi-level cell (MLC)-or-more method, and a controller configured to program first data in the first memory blocks by using the SLC method and then migrate the first data from the first memory blocks into the second memory blocks by using the MLC-or-more method, wherein the controller is further configured to read the first or second memory blocks according to a number of free blocks included in the first memory blocks, when the read request for the second memory block is received after the specific amount of time.

Controller and memory system having the controller

Embodiments of the present disclosure relate to a memory device and an operating method thereof. According to the embodiments of the present disclosure, when a read failure for a first read command among a plurality of read commands inputted from a memory controller occurs, the memory device may execute in an overlapping manner, a read retry operation for the first read command and a read operation for a second read command among the plurality of read commands.

Memory device and operating method thereof

Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. According to embodiments of the present disclosure, the memory system may calculate a time period Tthat is between a beginning of a program operation on a memory page included in the memory device and a suspension of the program operation, may calculate a time period Tthat is between the suspension of the program operation and a time point that is before a resumption of the program operation, may calculate, based on the time period Tand the time period T, a read offset voltage to be applied to the memory cell to mitigate the change of the threshold voltage distribution, and may store the read offset voltage in the memory page in the memory device before the resumption of the program operation. Accordingly, the memory system is able to improve the reliability of operations of suspending and resuming a program operation and to improve the performance of a read operation.

Growing community of inventors

Icheon-si, South Korea

Chan Young Oh