Samsung Electronics Co., Ltd.

Chan-yong Lee

Min-soo Jang

Jong-Ho Lee

Jung-Bae Lee

Tae-Young Oh

Hoi-ju Chung

Chul-Sung Park

Jung-Hwa Lee

Young-Hun Seo

Joo-sun Choi

Chi-wook Kim

Jung-Sik Kim

Cheol Su Kim

Jang-Woo Ryu

Gong-Heum Han

Tae-seong Jang

Tae-Seong Jang

Sang-Ho Shin

Sung-Min Yim

Sung-geun Do

Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.

Memory device for controlling refreshing operation

A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

Memory devices that perform masked write operations and methods of operating the same

An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.

Multi level antifuse memory device and method of operating the same

A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Semiconductor memory device having improved refresh characteristics

A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.

Semiconductor memory device having local sense amplifier

A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.

Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device

A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.

Method and apparatus for increasing data read speed in a semiconductor memory device

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Suwon-si, South Korea

Chan-yong Lee