Intel Corporation

Chan W Lee

Robert F Krick

Alan Beecher Kyker

Hitesh Ahuja

Glenn J Hinton

Per H Hammarlund

Joseph F Rohlman

William Alexander

Ashwani Kumar Gupta

David J Sager

Michael D Upton

Darrell D Boggs

Reynold V D'Sa

Gary L Brown

Adrian L Carbine

Roshan J Fernando

Richard A Weier

Vihang D Pandya

A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.

LRU cache replacement for a partitioned set associative cache

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

System and method for storing immediate data

Self modifying code is detected using a translation lookaside buffer in order to provide cache coherency. The translation lookaside buffer has physical page addresses stored therein over which snoops can be performed using the physical memory address of a store into memory. The translation lookaside buffer includes a content addressable memory which not only provides page translation but provides content addressability based on the physical page addresses stored therein. If a match occurs during a snoop using the translation lookaside buffer, it is possible that an SMC occurred within the page of locations stored in memory associated with the matched physical page addresses. To provide finer granularity than a page of addresses, FINE HIT bits are included with each entry in the cache associating information in the cache to portions of a page within memory. Snoop logic performs the comparison of the FINE HIT bits with the respective lower order bits of the physical address to determine if a self modifying code condition has occurred within the portion of memory that may be stored in the cache.

Method and apparatus for self modifying code detection using a translation lookaside buffer

A method and device are provided for reading data from a trace cache in a manner that reduces the time and power consumed by such an operation. A mini-tag is provided for comparing to a requested address to reduce the amount of data that must be read. Mini-tag read and compare operations may be performed in parallel to a full tag read operation, and a data read operation of only the data identified by a matching mini-tag may be performed in parallel to a full tag compare operation. A victim selection method for writing data into the trace cache is used to maintain the uniqueness of the mini-tags.

Multi-tag system and method for cache read/write

Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.

Processor instruction pipeline with error detection scheme

A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.

Method and system for bypassing a fill buffer located along a first instruction path

A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

Trace based instruction caching

A trace branch prediction unit includes a trace branch target buffer connected to a trace cache. The trace cache stores traces of micro-ops, with the micro-ops being stored non-sequentially. The trace branch target buffer generally reads a buffer entry corresponding to a particular trace line one clock cycle before the trace line is read to a processor. Using the entry, the trace branch target buffer predicts whether the trace cache should follow the existing trace or leave the trace. If the trace branch target buffer predicts that the trace cache should leave a trace, the trace branch target buffer provides a target address for a new trace. The trace branch target buffer also predicts when a trace is ending and provides a target address for the next trace.

Trace branch prediction unit

A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

Dual instruction buffers with a bypass bus and rotator for a decoder of

A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder. If a length-varying prefix and a matching length-varying opcode are both present in an instruction, processing in the fast carry chain circuitry is aborted, and processing in slow carry chain circuitry is started. The slow carry chain circuitry processes information from a subset of the input buffer at a time, and thus requires more than one iteration, with a different set of PLA inputs provided by a multiplexer upon each iteration. A SCC latch latches the output length marks from the slow carry chain circuitry and provides an output to the instruction decoder.

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Portland, OR, United States of America

Chan W Lee