Hynix Semiconductor Inc.

Skhynix Inc.

Chan Sun Hyun

Woo June Kwon

Myung Kyu Ahn

Jong Hoon Kim

Wan Soo Kim

Young Bin Ko

A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

Manufacturing method for semiconductor device having hole penetrating stack structure

A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Three-dimensional (3D) semiconductor device

A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.

Semiconductor device and method of manufacturing the same

The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.

Semiconductor device having stable structure and method of manufacturing the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating patterns having a stair structure and being alternately stacked, pad patterns connected to end portions of upper surfaces of the conductive patterns exposed through the stair structure, and a channel film penetrating the conductive patterns and the interlayer insulating patterns.

Semiconductor device and method of fabricating the same

In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semiconductor substrate. In an etch process of forming the contact plug, the passivation layer formed on sidewalls of the select lines is formed twice to protect the sidewalls of the select lines. Accordingly, the sidewalls of the select lines can be prevented from being damaged. Consequently, a process margin necessary to form a contact plug can be increased and, therefore, a smaller contact plug can be formed.

Method of forming a contact plug of a semiconductor device

A method of forming the gate patterns of a nonvolatile memory device comprises stacking a gate insulating layer and a first conductive layer over a semiconductor substrate; forming isolation hard mask patterns over the first conductive layer; etching the first conductive layer using the isolation hard mask patterns as etch barriers, thus exposing the gate insulating layer; etching the gate insulating layer using the isolation hard mask patterns as etch barriers, thus exposing the semiconductor substrate; after exposing the semiconductor substrate, forming a passivation layer on the sidewalls of the first conductive layers and on the sidewalls of the gate insulating layers; and etching the semiconductor substrate using the passivation layer and the isolation hard mask patterns as etch barriers, thus forming trenches in the semiconductor substrate.

Method of forming nonvolatile memory device

According to yet another embodiment, a method for forming a non-volatile memory device includes etching a substrate to form first and second trenches. The first and second trenches are filled with an insulating material to form first and second isolation structures. A conductive layer is formed over the first and second isolation structures and between the first and second isolation structures to form a floating gate. The conductive layer and the first isolation structure are etched to form a third trench having an upper portion and a lower portion, the upper portion having vertical sidewalls and the lower portion having sloping sidewalls. The third trench is filled with a conductive material to form a control gate.

Method of manufacturing flash memory device

A method of forming patterns of a semiconductor device comprising forming an auxiliary layer over an underlying layer comprising a cell region and a select transistor region, forming a first passivation layer over the auxiliary layer, wherein the first passivation layer blocks the auxiliary layer of the select transistor region and opens the auxiliary layer of the cell region, and forming a first photoresist pattern having a narrower width than the first passivation layer over (a) the first passivation layer and (b) second photoresist patterns, each having a narrower width than the first photoresist pattern, over an opening region of the auxiliary layer, wherein a gap between the first and second photoresist patterns is identical in width with a gap defined between the second photoresist patterns.

Method of forming patterns of a semiconductor device including forming spacers on sidewalls of auxiliary patterns and removing exposed auxiliary patterns

A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating layer, forming a mask layer over the second insulating layer of other region except a region in which the contact plugs are formed so that the damascene patterns are exposed through the region in which the contact plugs are formed, removing the etch barrier layer under the exposed damascene patterns using an etching process employing the mask layer, and removing the mask layer.

Method of forming damascene patterns of semiconductor devices

In a method of forming a dual damascene pattern of a semiconductor device, horns that occur while forming a trench constituting the dual damascene pattern are removed in an intermediate process of forming the trench. Thus, the source of particles, which occur due to the horns in a cleaning process performed after the dual damascene pattern is formed, may be removed. Accordingly, an increase of contact resistance due to particles may be prevented, and a reduction in the yield of semiconductor devices may also be improved.

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Icheon-si, South Korea

Chan Sun Hyun