Samsung Electronics Co., Ltd.

Chan-Suk Lee

Jin-Ho Kim

Se-Yong Oh

Cheol-Joon Yoo

Tae-Sung Yoon

Sung-Hwan Yoon

Sang-Hyeop Lee

Hee-Jin Park

Min-Keun Kwak

Cheul-Joong Youn

Tae-Duk Nam

A semiconductor package and a package mounting substrate can be joined using a conductive material column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. The insulating protective openings protect the solder column against stress faults to form reliable electrical connections and to support high-density electrical connections between the semiconductor package and the package mounting substrate.

Structure for joining a semiconductor package to a substrate using a solder column

The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.

Lead on chip semiconductor package

In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first semiconductor chip to the second semiconductor chip. The first conductor may be formed such that the first conductor does not extend beyond a periphery of the first semiconductor chip. The first conductor electrically connects at least one bond pad on the first semiconductor chip with at least one bond pad on the second semiconductor chip, and a redistribution pattern electrically connects the bond pad on the second semiconductor chip to a differently positioned bond pad on the second semiconductor chip.

Stacked offset semiconductor package and method for fabricating

A semiconductor package such as a bumped chip carrier (BCC) package has projections extending from a lower surface of a resin encapsulant. Each projection has a concave depression formed thereon. By reflowing a solder layer, external terminals are formed to cover the projections. An interface between the terminals and the projections increases in area, relative to conventional structures, because of the concave depressions. Therefore, the adhesive strength between the terminals and the projections also increases, and, when the BCC package is mounted on a next-level circuit board through the terminals, solder joint is also improved in reliability.

Bumped chip carrier package using lead frame and method for manufacturing the same

Growing community of inventors

Chungcheongnam-do, South Korea

Chan-Suk Lee