Himax Technologies, Inc.

Himax Media Solutions, Inc.

Chan-Shih Lin

Kuei-Lan Lin

Chien-Chang Lin

Shu-Hsien Chou

Yin-Her Su

Shao-Yung Su

A method of decoding and displaying video frames and an apparatus thereof are disclosed. The method includes indexing the first portion of a buffer with the first reference number, said first portion to be stored with the first reference frame; changing said first reference number to the second reference upon detecting the second reference frame to be stored in the second portion of said buffer; storing the third reference frame in the third portion of said buffer; and displaying said first reference frame associated with said second reference number, wherein storing said third reference frame in said third portion performs simultaneously with displaying said first reference frame.

Method and device for decoding and displaying video frames

A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.

Multi-format video decoder and related decoding method

Frame data stored in an external memory is partitioned into a plurality of macroblocks, and a plurality of access units each comprising at least one macroblock are provided. A plurality of frames are fetched from the external memory by loading the plurality of access units in a predetermined sequence. A current data for decoding a macroblock of the first access unit and a reference data for decoding a macroblock of the second access unit are loaded from the first access unit, and respectively mapped to a first memory group and a second memory group of a circular cache according to the frame width.

Data-mapping method and cache system for use in a motion compensation system

A bit-stream buffer controller for a video decoder includes a first FIFO, a second FIFO, and an interrupt controller. The first FIFO is configured to store an input bit-stream. The second FIFO is configured to store a payload extracted from the input bit-stream. The interrupt controller is configured to generate an interrupt signal according to a fullness status of the first FIFO and the second FIFO such that the video decoder may be switched to load the payload without checking the fullness status each time the payload is loaded.

Bit stream buffer controller and its method

A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer () that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic () that generates said check data by calculating one of said plurality of data outputted from said multiplexer.

Fast debugging tool for CRC insertion in MPEG-2 video decoder

An apparatus for processing a data stream having a hierarchical layer structure and including encoded data sets and raw data sets is provided. The apparatus includes a first processing circuit for generating an enable signal corresponding to a predetermined layer of the hierarchical layer structure when detecting that a data set of the data stream corresponds to the predetermined layer, and a second processing circuit coupled to the first processing circuit for detecting whether an identifier of the data set corresponds to one predetermined raw data set identifier when receiving the enable signal from the first processing circuit.

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Tainan, Taiwan

Chan-Shih Lin