Hughes Aircraft Company

Chan S Wu

Cheng P Wen

Cheng K Pao

Peter Chu

A microwave monolithic integrated circuit (MMIC) (40), includes a substrate (60), and an input bus (62), output bus (64), ground bus (66) and bias bus (68) formed as striplines of a four-line coplanar waveguide on the substrate (60) with the input bus (62) and output bus (64) disposed between the ground bus (66) and bias bus (68). A plurality of spatially distributed cascode amplifier units (43) are formed on the substrate (60), each including an input heterojunction bipolar transistor (HBT) (42) connected in a common-emitter configuration, and an output HBT (44) connected in a common-base configuration. The input HBT (42) has an emitter (E.sub.1) connected to the ground bus (66), a base (B.sub.1) connected to the input bus (62) and a collector (C.sub.1). The output HBT (44) has an emitter (E.sub.2) connected to the collector (C.sub.1) of the input HBT (42), a base (B.sub.2) connected to the bias bus (68) and a collector (C.sub.2) connected to the output bus (64). The distributed amplifier arrangement enables the HBTs (42,44) to operate with balanced electrical parameters and high thermal isolation and heat dissipation.

Microwave monolithic integrated circuit (MMIC) including distributed

The base-collector capacitance in a heterojunction bipolar transistor (HBT) (50) is reduced, thereby providing increased cutoff frequency and power gain, by eliminating a portion of a collector contact layer (54) which normally underlies a base electrode (66). A similar effect may be produced by forming the collector contact layer (54) such that it initially extends into the area (54c) under the base electrode (66), and subsequently rendering the collector contact layer (54) in this area (54c) semiinsulative by proton bombardment. A ballast resistor layer (70) is formed between an emitter layer (62) and an overlying emitter electrode (68) to prevent thermal runaway and hot spot formation. A plurality of the HBTs (50) may be arranged in a distributed amplifier configuration (80) including contact electrode bus lines (84,88) having a geometry designed to provide high thermal efficiency, and input and output circuit matching characteristics.

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Torrance, CA, United States of America

Chan S Wu