Himax Technologies, Inc.

Ncku Research and Development Foundation

Himax Semiconductor, Inc.

Oryx Holdings Pty Ltd.

Chan-Liang Wu

Ming-Cheng Chiu

Sheng-Jhih Jiang

Tsung-Yi Ho

Chien-Pin Chen

Po-Yang Tsai

Tz-Ian Hung

A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.

Semiconductor device having alignment mark

A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.

Method of resistor matching in analog integrated circuit layout

A floorplanning method for an analog integrated circuit layout is disclosed. A first-type block is defined as a movable and deformable block with rectangle constraint, and a second-type block is defined as a fixed-size block without rectangle constraint. Each block in the floorplan is classified to the first-type or the second-type block. In a shape determination stage, a target shape is determined among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap in the floorplan. In an overlap elimination stage, neighboring blocks of each said overlap are analyzed, the overlap being then eliminated by utilizing surrounding space, resulting in unused space in the floorplan. In an enlargement stage, the unused space is utilized for enlarging the first-type block.

Floorplanning method for an analog integrated circuit layout

A structure for preventing leakage of a semiconductor device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.

Structure for preventing leakage of a semiconductor device

An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.

Integrated circuit with a reduced pad bump area and the manufacturing method thereof

A triple operation voltage device including a first type substrate, a high voltage (HV) first type well, a second type well, a low voltage (LV) device well, and a middle voltage (MV) device well is provided. The HV first type well is disposed inside the first type substrate. The second type well is disposed inside the first type substrate to separate the HV first type well from the first type substrate. The LV device well and the MV device well are separately disposed inside the HV first type well by the separation of the HV first type well. The triple operation voltage device assists in reducing the space between the LV device well and the MV device well and improving the integration of integrated circuits.

Triple operation voltage device

A structure for preventing leakage of a high voltage device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.

Growing community of inventors

Tainan, Taiwan

Chan-Liang Wu