Samsung Electronics Co., Ltd.

Wisconsin Alumni Research Foundation

Snu Rdb Foundation

Chan-Kyung Kim

Chul-woo Park

Sang-beom Kang

Hong-Sun Hwang

Yun-sang Lee

Hyung-Rok Oh

Dong-hyun Sohn

Dong-seok Kang

Yongsik Youn

Sooho Cha

Hye-Jin Kim

Ho-Young Song

Nam Sung Kim

Jung Ho Ahn

Sang-Joon Hwang

Kee-Won Kwon

Eun-Seok Song

Young-Hoon Son

Seong-Il O

Soo-Ho Cha

Tae-joo Hwang

Hyung-rock Oh

Adrian E Ong

Dong-Min Kim

Jae-Youn Youn

Sung-Ho Park

Sang-Hoon Shin

Young-Nam Hwang

Su-a Kim

Jin-Min Kim

Sang-Kil Lee

Hyun-Sung Shin

Soon-Young Kim

Yong-Sik Park

Jae-Hong Min

DongSeok Kang

Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.

Memory device including arithmetic circuit and neural network system including the same

A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

Memory device supporting skip calculation mode and method of operating the same

A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

Memory module, memory device, and processing device having a processor mode, and memory system

A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.

Semiconductor package

A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Spin transfer torque magnetic random access memory for supporting operational modes with mode register

A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the Mand Mmetal layers of the memory device.

Method of reconfiguring DQ pads of memory device and DQ pad reconfigurable memory device

A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

On-chip resistance measurement circuit and resistive memory device including the same

A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.

Resistive memory device, memory system including the same and method of reading data from the same

A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same

A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

Semiconductor memory devices for alternately selecting bit lines

Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

Memory device, method of performing read or write operation and memory system including the same

A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.

Common source semiconductor memory device

Growing community of inventors

Hwaseong-si, South Korea

Chan-Kyung Kim