Samsung Electronics Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Chan-Kwang Park

Sang-Pil Sim

Tae-wan Lim

Ki-Yeol Byun

Seung-Ah Kim

Jae-Hwan Moon

Ki-Nam Kim

Soon-Moon Jung

Kwang-soo Kim

Wook-Hyun Kwon

Wook-hyun Kwon

Heon-Kyu Lee

Yo-Hwan Koh

Kwang-Myoung Rho

Seong-Min Hwang

Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

Semiconductor memory device and method of forming the same

Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

Multilevel integrated circuit devices and methods of forming the same

A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

Fabrication method and structure for providing a recessed channel in a nonvolatile memory device

A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.

Contactless nonvolatile memory device and method of forming the same

A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the active regions, and a common source line electrically connects the active regions between two word lines of word line pairs. A source strapping region is defined between the two word lines of the word line pairs. The source strapping region crosses multiple active regions.

Cell arrays of memory devices having extended source strapping regions

A method of manufacturing a semiconductor device, capable of securing an alignment margin between bit lines and a storage node contact is disclosed herein. The method includes: a depositing step of a first insulating layer on a semiconductor substrate of MOS structure; a forming step of a bit line pattern; a depositing step of a second insulating layer; a depositing step of sequentially a third and fourth insulating layers which have different etch rates; a masking and etching step of said fourth and third insulating layers to form T-shaped patterns in cross-sectional view; a forming step of polysilicon spacers at sidewalls of the T-shaped insulating patterns; a depositing step of a fifth insulating layer; a forming step of first photoresist mask pattern; etching steps of etching a predetermined portion of the fifth insulating layer, etching the T-shaped insulating layer pattern, etching the second insulating layer, etching the bit line pattern and etching the first insulating layer; a forming step of bit line contact; a depositing step of a sixth insulating layer; a forming step of second photoresist mask pattern for forming storage node contact hole on the sixth insulating layer and a forming step of a storage node contact hole by etching the predetermined portions of the sixth and fifth insulating layers, the T-shaped pattern, and the second and first insulating layer, sequentially.

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Seoul, South Korea

Chan-Kwang Park