Samsung Electronics Co., Ltd.

Chan-Joo Youn

Mun-Pyo Hong

Byung-Hoo Jung

Chang-Won Hwang

Joo-Hyung Lee

Joo-hyung Lee

Ju-hyung Lee

A double level gate layer with an undercut lower gate layer can be formed by using the etching rate difference between the upper gate layer and the lower gate layer in a polycrystalline Si type TFT LCD that has P-channel TFTs and N-channel TFTs. An LDD structure can be easily formed by using an upper gate layer as ion implant mask during the N-type ion implantation. LDD size is decided by the skew size between the upper gate layer and the lower gate layer. Furthermore, a photolithography step necessary for masking the ion implantation can be skipped.

Method for forming a TFT in a liquid crystal display

Disclosed is a thin film transistor (TFT) having a buffering pad layer and a method for manufacturing the same. This TFT is comprised of an active polysilicon pattern formed on a substrate. An oxide film is formed on the active polysilicon pattern. An intrinsic amorphous silicon pattern is formed on the oxide film and a metal pattern on the intrinsic amorphous silicon pattern. The intrinsic amorphous silicon layer serves as a buffering pad. The ion-implantation processes and heat processes are required if other types of silicon were used as a buffering pad.

Thin film transistor having a buffering pad layer for a liquid crystal

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Seoul, South Korea

Chan-Joo Youn