Samsung Electronics Co., Ltd.

Chan-Jo Lee

Seung-Keun Lee

Jeong-hyuk Choi

Yun-Heub Song

Joon-Sung Lee

Jae-sun Yun

A method for managing memory cells in a nonvolatile memory, such as a flash memory, includes detecting and intermediately programming fast-erased memory cells. All of the memory cells in a sector can then be erased.

Method for erasing memory cells in a nonvolatile memory

An improved method of fabricating a flash memory cell is disclosed. A tunnel oxide film is formed on active regions. A first conductive film and a protective film are sequentially formed on the tunnel oxide film. The protective film on the isolation film is selectively etched, thus forming a protective film pattern on the tunnel oxide film. A sacrificial conductive film is formed on the resultant structure. The sacrificial conductive film and the first conductive film pattern are over-etched until the sidewalls and the upper surface of the protective film pattern are exposed, thereby exposing the center of the isolation film and simultaneously forming a first conductive film pattern having sloped sidewalls. With the present invention, an electrical field is prevented from being concentrated in an area between a control gate electrode and a floating gate because the floating gate have a sloped sidewall profile instead of sharp edges. Also, the recession of an isolation film between adjacent floating gates can be significantly avoided, consequently suppressing the deterioration of isolation between adjacent cells.

Method of fabricating cell of flash memory device

A static random access memory device includes: a semiconductor substrate divided into a cell array portion and a periphery circuit portion; a first insulating layer for insulating devices formed on the substrate from a thin-film transistor; a conductive layer formed on the first insulating layer in the cell array portion, for supplying power; a buffer layer formed on the conductive layer in the cell array portion; a second insulating layer formed on the buffer layer in the cell array portion and on the first insulating layer of the periphery circuit portion; and a metal wiring pattern formed on the second insulating layer. A first portion of the metal wiring pattern connects to the conductive layer via a first contact hole which is formed passing through the second insulating layer and the buffer layer, thus exposing the conductive layer in the cell array portion. A second portion of the metal wiring pattern connects to the substrate via a second contact hole which is formed passing through the second insulating layer and the first insulating layer, thus exposing the semiconductor substrate in the periphery circuit portion or exposing a contact to a device in the semiconductor substrate in the cell array portion. The first and second portions of the metal wiring pattern may or may not connect to each other. The buffer layer prevents over-etching caused by the difference in the etched depth of the first and second contact holes which are concurrently formed, solving the problem of poor contact to the conductive layer from the metal wiring pattern formed on the second insulating layer.

Static random access memory device manufacturing method

A static RAM which is a CMOS static RAM having first and second load transistors, first and second driver transistors, and first and second switching transistors in one memory cell includes: a laminated structure of a first polysilicon layer, a silicide layer and a second polysilicon layer, forming the gate regions of the second load and driver transistors in a body; an interconnection layer comprising a laminated structure of the silicide layer and the second polysilicon layer to form a p-n junction between the drain regions of the first load and driver transistors; and one contact for making the gate regions and the interconnection layer in a body by the second polysilicon layer.

Cell structure of an improved CMOS static RAM and its fabrication method

Interconnection structures for integrated circuits include first and second spaced apart active regions in an integrated circuit at a face thereof and a recessed isolation region in the integrated circuit, between the first and second spaced apart active regions and recessed beneath the face. A first conductive layer is included on the recessed isolation region. The first conductive layer extends between the first and second spaced apart active regions beneath the face, and electrically connects the first and second spaced apart active regions beneath the face. Accordingly, high density isolation regions and interconnection regions for the first and second spaced apart active regions are provided. A second conductive layer is preferably included on the face, extending from on the first active region onto the first conductive layer and onto the second active region. The interconnect structures may be formed by forming an isolation region in a face of an integrated circuit substrate, and first and second spaced apart active regions in the integrated circuit substrate at the face. A portion of the isolation region is removed, to form a recessed isolation region. A first conductive layer is formed on the recessed isolation region such that the first and second spaced apart regions and the first conductive layer are electrically interconnected beneath the face. A second conductive layer is formed on the face, extending from on the first active region onto the first conductive layer and onto the second region.

Interconnection structures for integrated circuits including recessed

Methods of forming semiconductor switching devices include the steps of separating refractory or group VIII metals to be used on electrodes and contact regions from each other, so that subsequent conversion of these metal layers to metal silicide layers will not result in the formation of silicide bridge defects ('shorts'). In particular, a method of forming a semiconductor switching device is provided that includes the steps of forming an electrode on a semiconductor substrate and then forming a first metal layer having a first thickness on the electrode. A contact region of first conductivity type is also formed in the semiconductor substrate and then a second metal layer having a second thickness, less than the first thickness, is formed on the contact region. The first and second metal layers are then simultaneously converted to first and second metal silicide layers using a thermal treatment step. Moreover, prior to performing the conversion step, the first and second metal layers are electrically insulated from each other to prevent the likelihood of formation of bridge defects which may result when residues of metal silicide are formed on the substrate. In addition, the thicknesses of each of the metal layers is preferably chosen so that careful control of the final thicknesses of the metal silicide layers can be obtained to optimize the electrical characteristics of the switching device.

Growing community of inventors

Seoul, South Korea

Chan-Jo Lee