Skhynix Inc.

Chan Hui Jeong

Hyung Jin Choi

Se Chun Park

Dong Hun Kwak

Suk Hwan Choi

Gwi Han Ko

Chan Keun Kwon

Chan Sik Park

Jin Yeop Kim

A memory device includes: memory cells connected between a common source line and bit lines; a source line driver for applying a common source line voltage to the common source line and then floating the common source line; and a program operation controller for controlling the source line driver to change a length of a floating period in which the common source line is floated, based on a degree to which a program operation on the memory cells is performed.

Memory device and operating method of the memory device for reducing power consumption for program operation

A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines and a voltage generating circuit for selectively outputting a program voltage and a verify voltage; and a control circuit configured to control the peripheral circuit to perform a plurality of program loops each including a program voltage apply operation and a verify operation. Each of the plurality of page buffers may include: a first latch for storing a verify result according to the verify operation of an nth program loop among the plurality of program loops; and a second latch for storing a verify result according to the verify operation of an (n−1)th program loop among the plurality of program loops.

Memory device, operating method of memory device, and memory system

The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a fail bit detection operation on memory cells selected from among the plurality of memory cells. The control logic may control the peripheral circuit to set target parameters related to a main operation based on a comparison result between a fail bit detection time measured in the fail bit detection operation and a reference time, and perform the main operation on the selected memory cells based on the target parameters.

Memory device and method of operating the same

A memory device includes: a plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops each including a program voltage apply operation of applying a program voltage to selected memory cells, and a verify operation of verifying a program state of the selected memory cells; and a control logic configured to control the peripheral circuit to apply program voltages increasing in a step-wise manner by a first step voltage in program loops in a first state, and increasing by a second step voltage that is lower than the first step voltage in program loops in a second state that occur after the program loops in the first state. The first state and the second state of the program loops are determined based on when a verify operation on a program state having a highest threshold voltage is performed.

Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device

The present technology may include a voltage generation circuit configured to generate a plurality of voltages in response to at least one voltage control signal, and control logic configured to generate the at least one voltage control signal in order to adjust at least one of an under drive time and an under drive offset during an under drive operation of a semiconductor apparatus according to a temperature information signal and a pre-stored temperature characteristic signal of the semiconductor apparatus.

Under drive control circuit and semiconductor apparatus including the under drive control circuit

A memory device includes memory cells connected to a plurality of word lines. The memory device also includes a read operation performer configured to perform a read operation of applying an equalizing voltage to the plurality of word lines and applying a read voltage to a selected word line. The memory device further includes a fail cell counter configured to count a number of on cells among selected memory cells connected to the selected word line at each of time points. The memory device additionally includes a read operation controller configured to control the read operation performer to determine a length of an evaluation period based on a result of comparing the number of on cells at each of the time points, and configured to sense a voltage of bit lines respectively connected to the selected memory cells after the evaluation period elapses from the time.

A memory device includes a precharge time information storage for storing information on a first precharge time for which a bit line control signal is applied and a second precharge time for which a source line control signal is applied, which are determined according to a degree to which a program operation is performed. The memory device also includes a precharge voltage controller for providing the bit line control signal and the source line control signal respectively to page buffers and a source line driver for a longer precharge time selected from the first precharge time and the second precharge time in the program operation.

Nonvolatile memory device including selective bit line and source line precharge times and operating method thereof

A power circuit includes a plurality of regulators and a plurality of in-rush current controllers. The plurality of regulators is coupled to an external power voltage and configured to adjust a level of an input voltage to generate a plurality of internal power voltages. The plurality of in-rush current controllers is configured to provide the input voltage to the plurality of regulators, the input voltage corresponding to an increasement voltage. The increasement voltage has a level rising at a preset rate until the plurality of internal power voltages all reach a target level.

Apparatus for controlling in-rush current and an operation method thereof

The present technology relates to a voltage supply circuit, and the voltage supply circuit according to the present technology includes a signal generation circuit configured to generate an active mode enable signal according to a chip selection signal provided from an external device, and generate a standby mode enable signal using an external voltage provided from the external device, an active voltage regulator configured to receive the active mode enable signal and output an active mode operation voltage when the active mode enable signal is in a high state, and a standby voltage regulator configured to receive the active mode enable signal and the standby mode enable signal, output a standby mode operation voltage while the standby mode enable signal is in the high state, and output a voltage lower than the standby mode operation voltage when the active mode enable signal is in the high state.

Voltage supply circuit with a voltage regulator

A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.

Semiconductor apparatus with program operation control

An operating method of a non-volatile memory device includes simultaneously performing a program operation on a plurality of selection transistors included in a plurality of cell strings each including a corresponding selection transistor of the selection transistors and a plurality of memory cells, each of the cell strings being coupled between a common source line and a corresponding bit line of a plurality of bit lines; sequentially performing verification operations on respective groups of the selection transistors, the groups being coupled to respective selection lines; and sequentially storing results of the verification operations into respective data latch circuits within each of a plurality of page buffers coupled to the bit lines.

Nonvolatile memory device including selection transistors and operating method thereof

A memory device, and a method of operating the same, includes a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, a weak word line information storage configured to store information about a weak word line among the plurality of word lines, and a program operation controller configured to control the peripheral circuit such that the program operation is performed in a first program mode or a second program mode depending on a result of determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line by comparing word lines based on the information about the weak word line.

The present disclosure relates to an electronic device. A memory device includes a plurality of memory cells coupled to a plurality of word lines, a voltage generator generating program-related voltages to be applied to the plurality of word lines, an address decoder transferring the program-related voltages to the plurality of word lines, and an operation controller controlling the voltage generator and the address decoder to apply a program voltage to a selected word line among the plurality of word lines, a second pass voltage to adjacent word lines neighboring the selected word line, a first pass voltage to remaining word lines except for the selected word line and the adjacent word lines, and to apply a ground voltage to the selected word line and the first pass voltage to the adjacent word lines during a first period.

Memory device and operating method thereof

An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

Internal voltage generation circuit and semiconductor memory apparatus including the same

A memory device according to the present technology includes a memory cell array configured to include planes having a plurality of memory cells, a page buffer connected to at least one memory cell among the memory cells through a bit line and configured to perform a sensing operation of reading data stored in the at least one memory cell connected to the bit line, a common reference voltage generator configured to generate a common reference voltage, a plurality of merged buffers configured to generate a reference signal using the common reference voltage, and control logic configured to control an operation of the common reference voltage generator and the merged buffers so that page buffer control signals generated based on the reference signal are supplied to the page buffer.

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Gyeonggi-do, South Korea

Chan Hui Jeong