Qualcomm Incorporated

Chan Hong Park

Liang Zhao

Mohammad Bagher Vahid Far

Abbas Komijani

Beomsup Kim

Cheng-Han Wang

Le Nguyen Luong

Charles James Persico

Jeongsik Yang

Yi Zeng

Jin-Su Ko

Koorosh Akhavan

Sang-Oh Lee

Emanuele Lopelli

Yongwang Ding

ByungWook Min

Hee Choul Lee

Aspects described herein include devices and methods for smart ultra wideband transmissions. In one aspect, an apparatus includes pulse generation circuitry configured to output a plurality of transmission (TX) pulse samples at a selected signal sample rate, where each pulse sample of the plurality of TX pulse samples comprises a value associated with a pulse amplitude at a corresponding sample time The apparatus includes a plurality of power amplifier (PA) cells, with each PA cell of the plurality of PA cells comprising a corresponding current source and associated gates, and where the associated gates of a PA cell are selectable to configure an on state and an off state. Logic circuitry of the apparatus is configured to set the on state or the off state for each PA cell.

Ultra wideband transmitter

An advantageously fast and asynchronous interface is disclosed for the tuning of an RF frontend. The interface transmits a tuning word to the RF frontend that controls a tuning of the RF frontend responsive to a channel index.

Tunable RF frontend

Certain aspects of the present disclosure provide voltage regulating circuits which are power efficient, low noise, and substantially insensitive to changes in process technology, power supply voltage, and temperature. Such circuits may be used to provide the regulated voltage for a voltage-controlled oscillator (VCO), for example, as found in a radio frequency front end (RFFE). One example voltage regulating circuit generally includes a current source configured to supply or sink a reference current and a current mirror having a bias branch and a main branch, wherein the bias branch is connected with the current source, wherein the main branch includes a source follower to provide the regulated voltage, and wherein the reference current is available at a node for the regulated voltage.

Power-efficient, low-noise, and process/voltage/temperature (PVT)&#x2014;insensitive regulator for a voltage-controlled oscillator (VCO)

System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

System for I-Q phase mismatch detection and correction

Techniques for writing to registers associated with MIMO signal paths are disclosed. In an embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.

Delta writing scheme for MIMO signal paths

A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.

DC offset calibration

A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A programmable charge pump current is tuned to the calculated first charge pump current.

Growing community of inventors

San Jose, CA, United States of America

Chan Hong Park