Intel Corporation

Chan-Hong Chern

Robert S Chau

Leopoldo D Yau

Chia-Hong Jan

Paul A Packan

Stephen T Chambers

Kevin R Weldon

Brian J Brown

Shahriar S Ahmed

Lawrence N Brigham

Robert F Hainsey

Robert J Stoner

Todd E Wilke

Binny P Arcot

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Transistor with ultra shallow tip and method of fabrication

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

Transistor with low resistance tip and method of fabrication in a CMOS

A method of forming a thin, robust nitrided oxide layer. The process results in a manufacturable, uniform, low-defect density, reliable nitrided oxide that may be used as a gate dielectric, as a portion of a spacer, or as a portion of a trench isolation. First, a substrate is oxidized in a chlorinated dry oxidation followed by a low temperature pyrogenic steam oxidation. Next, a low temperature ammonia anneal is performed, followed by a high temperature anneal in an inert ambient.

Manufacturable dielectric formed using multiple oxidation and anneal

A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Integrated dual layer emitter mask and emitter trench for BiCMOS

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Method of making emitter trench BiCMOS using integrated dual layer

A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.

Growing community of inventors

Portland, OR, United States of America

Chan-Hong Chern