Taiwan Semiconductor Manufacturing Comp. Ltd.

Chan-Hong Chern

Chih-Chang Lin

Ming-Chieh Huang

Fu-Lung Hsueh

Tao Wen Chung

Yuwen Swei

Tsung-Ching Huang

Min-Hsiang Hsu

Tien-Chun Yang

Weiwei Song

Tsung-Ching (Jim) Huang

Lan-Chou Cho

Kun-Lung Chen

Chiang Pu

Mark Chen

Yi-An Lai

Chewn-Pu Jou

Stefan Rusu

Cheng-Hsiang Hsieh

Steven Swei

Feng-Wei Kuo

King-Yuen Wong

Tysh-Bin Liu

Chun Lin Tsai

Ming-Cheng Lin

Chu Fu Chen

Mei-Hui Huang

Chih-Tsung Shih

Jun-De Jin

Min-Shueh Yuan

Kuoyuan Hsu

Tien Chun Yang

Bryan David Sheffield

Jing Jing Chen

Li-Chun Tien

Huan-Neng Chen

Derek C Tao

Ming Hsien Tsai

Jacklyn Chang

Chun-Lin Tsai

Chun-Yi Yang

Cheng-Tse Tang

Yung-Jr Hung

Tzu Ching Chang

Tysh-Bin Lin

Julie Tran

Ruo-Rung Huang

Yu-Ann Lai

Yue-Der Chih

Kuoyuan (Peter) Hsu

David Barry Scott

Tao-Wen Chung

Tzu-Ching Chang

Chih-Hua Wang

Tao Wen (David) Chung

Ming-Chich Huang

Pen Chieh Yu

Various embodiments of the present disclosure are directed towards an optical module including a first waveguide and a bypass waveguide. The first waveguide laterally extends in a first direction. The first waveguide comprises a first waveguide body segment and a first waveguide coupler structure. A transverse waveguide laterally extends in a second direction different from the first direction. A first dielectric layer is disposed over the first waveguide and the transverse waveguide. A bypass waveguide overlies the first dielectric layer and laterally extends in the first direction. The bypass waveguide comprises a bypass body segment and a first bypass coupler structure. At least a portion of the first bypass coupler structure overlies the first waveguide coupler structure. The bypass body segment overlies at least a portion of the transverse waveguide.

Bypass wavguide configured to facilitate inter-level optical coupling in optical module

A latch circuit includes first and second supply nodes having a first voltage value and a second voltage below the first voltage value, first and second input nodes, first and second output nodes, a first switch coupled between the first and second output nodes and turned on and off responsive to first and second clock signal states, first and second transistors coupled between the respective second and first output nodes and the second supply node. A second switch is coupled between a first transistor gate and the first input node, a third switch is coupled between a second transistor gate and the second input node, and each is turned on and off responsive to the first and second states. During the first state, one of the first or second transistors is part of a low resistance path from the first power supply node to the second power supply node.

Latch circuit and method of operating the same

A semiconductor device includes a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound material; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain electrode. The semiconductor device further includes a plurality of test structures, wherein each of the test structures, including a first metal pattern and a second metal pattern, emulates at least one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.

Gallium nitride-based devices and methods of testing thereof

A semiconductor package includes a photonic die having a first side and a second side opposite to each other. The semiconductor package includes an electrical die having a third side and a fourth side opposite to each other. The first side of the photonic die faces the third side of the electrical die. The photonic die has an index matching material extending from a surface of the photonic die on the second side into the photonic die.

Integrated packages having electrical devices and photonic devices and methods of manufacturing the same

A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.

Gallium nitride-on-silicon devices

An optical phase-shifting device includes a ribbed waveguide portion on an insulating layer, the waveguide portion having a p-n or p-i-n junction extending in a longitudinal direction and having a height. A pair of slab portions are disposed adjacent the waveguide portion, one on each side of the ribbed waveguide portion and on the insulation layer. The slab portion have higher doping concentrations than the respective doping concentrations in the ribbed waveguide portion. At least a portion of each slab portion has a height increasing with distance from the waveguide portion, with the slab height being smaller than that of the waveguide portion at the junction between the waveguide portion and slab portion. A pair of contact portions are formed adjacent the respective slab portion and further away from the waveguide portion. A portion of each contact portion can also have a height varying with distance from the waveguide portion.

Waveguide structure

A semiconductor structure including a semiconductor waveguide layer over a second dielectric layer and between sidewalls of a first dielectric layer. A first cladding layer is between the sidewalls of the first dielectric layer and directly over the semiconductor waveguide layer. A second cladding layer is between sidewalls of the second dielectric layer and directly under the semiconductor waveguide layer. A difference between a refractive index of the semiconductor waveguide layer and a refractive index of the first cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the first dielectric layer. A difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second dielectric layer.

Cladding structure for semiconductor waveguide

A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.

Semiconductor devices and circuits with increased breakdown voltage

A method of fabricating a device involves forming a plurality of structures, such that each structure of the plurality includes a substrate and an epitaxial layer on the substrate. The epitaxial layer and the substrate have a lattice mismatch. The method further includes forming an electrical contact on the epitaxial layer of a selected structure of the plurality of structures and performing a current leakage measurement quality control test for the selected structure of the plurality of structures through the electrical contact. The method also involves forming a device on each of the remaining structures of the plurality of structures if the selected structure passed the leakage measurement quality control test or discarding each of the remaining structures of the plurality of structures if the selected structure did not pass the leakage measurement quality control test.

Quality detection method and apparatus

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

Structures for providing electrical isolation in semiconductor devices

A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

Heterogenous integration scheme for III-V/Si and Si CMOS integrated circuits

Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle. In one embodiment, the system includes a square wave generator and a logic device. The square wave generator is configured to delay a input square wave signal to generate a plurality of square wave signals. The logic device is configured to perform a logic operation to two of square wave signals of the plurality of square wave signals, which in turn generates the PWM signal having a duty cycle corresponding to the two square wave signals.

Pulse width control apparatus and method

Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same

An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.

Optical device for coupling light and method for fabricating the same

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Optical waveguide apparatus and method of fabrication thereof

Growing community of inventors

Palo Alto, CA, United States of America

Chan-Hong Chern