Samsung Electronics Co., Ltd.

Chan Ho Yoon

Jun Jin Kong

Kyoung Lae Cho

Pil Sang Yoon

Young Jin Cho

Dong Hyuk Chae

Hyun Ju Yi

Jun Ho Choi

Seok-Won Ahn

Nam Phil Jo

Hyeok Jun Choe

Kil Hwan Kim

Jung Hyun Hong

Seok Won Ahn

Bum Seok Yu

Kwang Ho Yoo

Young Geon Yoo

Seung Chul Ryu

Eun Cheol Kim

A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.

Reconfigurable storage controller, storage device, and method of operating storage device

A scale-out device to control a group of non-volatile memory devices from among a plurality of non-volatile memory devices at a data storage device, includes a buffer and a scale-out controller. The buffer is configured to store address mapping information for the group of non-volatile memory devices, the group of non-volatile memory devices being a portion of the plurality of non-volatile memory devices at the data storage device. The scale-out controller is configured to control operation of only the group of non-volatile memory devices according to the address mapping information stored at the buffer.

Data storage devices, having scale-out devices to map and control groups on non-volatile memory devices

Data storage devices having scale-out devices to map and control groups of non-volatile memory devices

The data storage device includes scale-out storage devices and a controller configured to assign commands to the scale-out storage devices and re-assign the commands assigned to the scale-out storage devices based on state information output from a first scale-out storage device among the scale-out storage devices. Each of the scale-out storage devices includes a volatile memory device, a non-volatile memory device, and a scale-out controller configured to control the volatile memory device and the non-volatile memory device.

Data storage device that reassigns commands assigned to scale-out storage devices and data processing system having the same

A data storage device and a data processing system having the same are disclosed. The data storage device includes a nonvolatile memory and a controller, coupled to the nonvolatile memory, configured to receive first and second commands generated by a host and control an operation of the nonvolatile memory in response to the first command. The controller includes a core configured to receive and process the first command, a trace circuit corresponding to the core and configured to generate and output first data, based on pieces of information generated while the core processes the first command, and a trace controller configured to control output of the first data and second data differing from the first data, based on a result of performing at least one authentication control operation corresponding to the second command.

Data storage device and data processing system having the same

A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

Raid-6 data storage device and data processing system including the same

A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

Data compression devices, operating methods thereof, and data processing apparatuses including the same

A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

Memory system with error correction decoder architecture having reduced latency and increased throughput

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Seoul, South Korea

Chan Ho Yoon