Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Soongsil University

Hyundai Motor Company

Korea University Research and Business Foundation

Chan-Ho Lee

Ju-Yong Kim

Sung-Chul Lee

Jin-Goo Ahn

Man-Seok Han

Yong-Kul Lee

Jin-Kwang Kim

Dong-Myung Suh

Leonid Gorobinskiy

Dong-Uk Lee

Hyun-Soo Chung

Jong-Hoon Jung

Dong-Wook Seo

In-Gyu Park

Myeong-soon Park

Tae-hyung Kim

Jeung-Joo Lim

Eun-Kyoung Lim

Jae-Hoon Lee

Hyun Sook Kim

Tae-Joong Song

Hyun-Chul Kim

Seong-Jin An

Jae-Bong Chun

In-Hyuk Son

In-Young Lee

Jun-Sik Kim

Alexey Alexandrovichserov

Gyu-Hong Kim

Seung-Mo Kim

Woo-Kwang Lee

Tae-hyoung Kim

Jae-Seung Choi

Hyun Soh

Sang-Jun Kong

Bong-Kyoung Park

Hyun-Su Choi

Young-eun Kim

Han-Sung Ryu

Jong-ok Kim

Soung-Hoon Sim

Young-Tae Jin

Min-Jung Oh

Myeong-Ju Ha

Dong-Yun Lee

Chang-Bong Lee

Hyeong-Mo Yang

Wan-jung Kim

Kie Hyun Nam

Naum Feygenson

Jin-Kuk Bae

Sung-Ii Chang

Byung-Sub Park

Young-Gyun Im

Kie-Hyun Nam

Jae-Sung Bang

Noboru Sato

Jun-sic Kim

Gorobinskiy Leonid

Nok-Hyun Ju

Jun-Sang Yoo

Noboru Sata

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Semiconductor chip including chip pad, redistribution wiring test pad, and redistribution wiring connection pad

An image processing method and apparatus is disclosed, where the image processing method includes receiving an image including frames captured over a time period in an illumination environment including alternating current (AC) light, estimating a specular chromaticity and a diffuse chromaticity of the image based on the frames, determining a weight of each of the specular chromaticity and the diffuse chromaticity based on a frame of the frames, and correcting the image based on the specular chromaticity, the diffuse chromaticity, the weight of the specular chromaticity, and the weight of the diffuse chromaticity.

Image processing method and apparatus

An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

Integrated circuits including multi-layer conducting lines

A semiconductor chip includes a substrate having a low-k material layer. An electrode pad is disposed the substrate. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.

Semiconductor chip including a bump structure and semiconductor package including the same

A method is provided for managing data in an electronic device, the method including: detecting a request for tagging a data record; selecting a portion of the data record in response to the request; identifying a content item based on the selected portion of the data record; and associating the content item with the data record.

Method and apparatus for managing data

A 4 wheel drive vehicle removes sense of shift difference through an acceleration shift control mode, and the acceleration shift control mode transfers an independent other drive shaft input torque to a drive shaft not connected to a transmission with respect to a transmission input torque transferred to a drive shaft connected with the transmission, so that a vehicle acceleration in an actual shift section connecting between a fore-section and post-section of the shift can be maintained to be equal to the vehicle acceleration of the fore-section and post-section of the, thereby overcoming the transfer torque change, which is not overcome in a conventional slip control method, speed control method and time control method, when transferring a torque to the drive wheels in the actual shift section and realizing the shift quality without the sense of shift difference.

Method for controlling sense of shift difference and 4-wheel drive vehicle applying the same

A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.

Scan chain circuit and integrated circuit including the same

A method of verifying a layout of a mask read only memory (ROM) includes: receiving source ROM code, bitmap data, and layout design data of the mask ROM; generating coordinate data of a bit determining unit based on the layout design data; and determining an error cell based on the coordinate data of the bit determining unit, the bitmap data, and the source ROM code.

Method of verifying layout of mask ROM

A metal-oxide-semiconductor field-effect transistor device includes a first active area, a first gate electrode configured to cross the first active area and extend in a Y direction, and define a first source area and a first drain area, first gate contacts disposed on the first gate electrode to align on a first virtual gate passing line extending in the Y direction, first source contacts disposed on the first source area to align on a first virtual source passing line extending in the Y direction, and first drain contacts disposed on the first drain area to align on a first virtual drain passing line extending in the Y direction, wherein at least one of the first drain contacts is disposed to align on any one of first virtual X-straight lines configured to pass between the first source contacts and extend parallel in an X direction perpendicular to the Y direction.

Layouts and vertical structures of MOSFET devices

Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed.

Semiconductor chip and method of controlling memory

A rechargeable battery according includes a plurality of electrode assemblies including a first electrode assembly and a second electrode assembly, a case housing the plurality of electrode assemblies, a cap assembly coupled to the case, and a first safety member including a first conductive plate between the first electrode assembly and the case, a second conductive plate between the second electrode assembly and the case, and a safety fuse between the first conductive plate and the second conductive plate and coupling the first and second conductive plates together.

Rechargeable battery having safety member

Disclosed herein are an apparatus and method for controlling memory. The apparatus includes a memory access request buffer unit, a memory access request control unit, and a bank control unit. The memory access request buffer unit determines and stores memory access request order so that the plurality of memory access requests is processed in the order of input except that memory access requests attempting to access the same bank and the same row are successively processed. The memory access request control unit reads the memory access requests from the memory access request buffer unit in the determined order, distributes the memory access requests to banks, and transfers the memory access requests to memory. The bank control unit stores a preset number of memory access requests in each of buffer units for respective banks, and controls the operating state of each of the banks.

Apparatus and method for controlling memory

Growing community of inventors

Suwon-si, South Korea

Chan-Ho Lee