Samsung Electronics Co., Ltd.

Chan-Hee Jeon

Han-Gu Kim

Ki-Tae Lee

Il-Ryong Kim

Eun-Kyoung Kwon

Woo-Jin Seo

Kyoung-Sik Im

Hyun-Jun Choi

In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

Semiconductor device and method for fabricating the same

Semiconductor device including an extended impurity region

A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.

Transistor with EOS protection and ESD protection circuit including the same

Growing community of inventors

Hwaseong-si, South Korea

Chan-Hee Jeon