Texas Instruments Corporation

Cosmic Circuits Private Limited

Other

Chakravarthy Srinivasan

Shankaranarayana Karantha

Tonmoy Shingal

Prakash Easwaran

Saumitra Singh

Rupak Ghayal

Prasenjit Bhowmik

Pawan Kumar Gupta

Sundararajan Krishnan

Sumanth Chakkirala

Kiran Godbole

Prasun Kali Bhattacharya

Chandrashekar Lakshminarayanan

Mukesh Khatri

Sanjeeb Kumar Ghosh

Venkatesh Teeka Srinvasa Setty

A spread-spectrum switching regulator for eliminating modulation ripple includes high gain amplifier that is responsive to reference voltage and feedback voltage of feedback loop to generate differential voltage, the feedback voltage being one of output voltage of the spread-spectrum switching regulator and a fraction of the output voltage; compensation circuit, coupled to the high gain amplifier, that maintains stability of the feedback loop to generate error level voltage in response to differential voltage; ramp generator that generates ramp waveform with slope adaptable to switching frequency to maintain duty cycle at constant value; pulse width modulator, coupled to compensation circuit and ramp generator, that compares error level voltage and ramp waveform to generate pulsed waveform; driver circuit, coupled to pulse width modulator, that drives the pulsed waveform to alternately switch a pair of transistors; and LC network, coupled to the pair of transistors, to average pulsed waveform to the output voltage.

Spread-spectrum switching regulator for eliminating modulation ripple

A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.

Processes, circuits, devices, and systems for concurrent dual memory access in encryption and decryption

Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions.

Efficient switch cascode architecture for switching devices

A wireless communications device () has a digital section () and a radio frequency section (). The digital section () does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine () is shared by the setup and execution iterations. Two or more memory units () segregate the set of data, the predetermined size of the set of data in the memories () combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (). Dirty bits () are accessible at addresses corresponding to addresses in the memory. A selector circuit () has a selector output selectively coupled to an address line, and to a data line. The selector circuit () responds to a state on a dirty bit line (db) to couple data bits related to the address bits themselves from the address line () to the selector output (). Other circuits and methods of manufacture and operation are also disclosed.

Process, circuits, devices, and systems for encryption and decryption and other purposes, and process making

A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

System and method for reducing power dissipation in an analog to digital converter

Processes, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making

An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.

Error correction architecture to increase speed and relax current drive requirements of SAR ADC

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Bengaluru, India

Chakravarthy Srinivasan