Xilinx, Inc.

Other

Chakravarthy K Allamsetty

Carl H Carmichael

Conrad A Theron

Jeffrey V Lindholm

Donald H St Pierre, Jr

Arun K Mandhania

Thach-Kinh Le

A system and method for testing a circuit implemented on a programmable logic device. A host processor is coupled to the programmable logic device via an interface device, which has a plurality of signal pins for configuring the programmable logic device. Selected pins of the interface device are connected to selected input pins of the programmable logic device. Test vectors from the host processor are applied to the selected input pins of the programmable logic device via the interface device, and the states of one or more signals appearing on one or more output pins of the device are analyzed.

System and method for testing a circuit implemented on a programmable logic device

A system and method utilize bitmaps for verifying configuration of a programmable logic device (PLD). A configuration bitstream containing configuration commands and data is converted to a configuration bitmap. The configuration bitstream is downloaded to PLD, thus programming the PLD. Readback commands and data read back from the PLD are used to generate a readback bitstream. The readback bitstream is then converted to a readback bitmap. Bits at corresponding cell locations in the readback bitmap and the configuration bitmap are compared. An error signal is output if the bits are different. In one embodiment, a mask bitmap is generated to indicate which cell locations are non-configuration memory cells and thus need not be compared.

System and method for verifying configuration of a programmable logic device

A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.

System and method for reading data from a programmable logic device

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Milpitas, CA, United States of America

Chakravarthy K Allamsetty