Intel Corporation

Chakrapani Pathikonda

Matthew A Fisch

Javed Sabir Barkatullah

Michael W Rhodehamel

Nitin V Sarangdhar

Jeff Wight

A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Core clock correction in a 2/n mode clocking scheme

A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Core clock correction in a 2/N mode clocking scheme

Apparatus for generating bus clock signals with a 1/N characteristic in

Method and apparatus for generating 2/N mode bus clock signals

Auto-configuration support for a multiple processor-ready pair or FRC-master/checker pair is achieved through the use of an initialization signal issued to each agent on a bus during system reset. The agents on the bus are interconnected using a rotating interconnect scheme which causes each agent to sample a signal issued from another agent on a pin different from the pin on which the other agent issued the signal. When operating in FRC-master/checker mode, the checker agent operates as if it were the master agent, thereby checking the operation of the master agent. The initialization signal modifies the input and or output lines connected to the pins of the checker agent based on this rotating interconnect scheme, thereby ensuring the checker agent properly checks the master agent's operation.

Auto-configuration support for multiple processor-ready pair or

Pad cells for a 2/N mode clocking scheme

Method and apparatus for preventing logic glitches in a 2/n clocking

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Beaverton, OR, United States of America

Chakrapani Pathikonda