Ati International Srl

Chak Cheung Edward Ho

Oleg Drapkin

Gordon Caruk

Carl K Mizuyabu

Hugh Chow

Ray Chau

A signal phase shifting circuit shifts the phase of an input signal, such as a STROBE signal, based on a reference signal, such as a CLOCK signal, to facilitate, for example, receiving of double data rate data. The signal phase shifting circuit includes a reference signal period dividing circuit having a feedback delay matching array operatively coupled to one of a plurality of voltage control delay lines. This signal phase shifting circuit also includes a variable delay circuit that provides a phase shifted output signal, such as a phase shifted STROBE signal, that includes a delay stage in a phase shifted output signal drive buffer coupled to the delay stage, such as a voltage control delay line. The feedback delay matching array includes a plurality of serially coupled buffer stages operatively coupled to compensate for delay variations associated with the phase shifted output signal drive buffer in the variable delay circuit.

Apparatus for synchronization of double data rate signaling

In one embodiment of the present invention, a 10-bit encoded video word is received and stored as two five-bit representations. One of the stored five-bit representations is selected by a multiplexor and provided to a parallel-to-serial converter. The parallel-to-serial converter receives control signals from a multiphase clock. Specifically, the multiphase clock provides a five-phase multi-phased clocks in order to control the parallel-to-serial converter. The serial-to-parallel converter provides a 10-bit serial representation of the 10-bit encoded input.

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Markham, Canada

Chak Cheung Edward Ho