Samsung Electronics Co., Ltd.

Sansumg Electronics Co., Ltd.

Chajea Jo

Hyoeun Kim

Sang-Uk Han

Taeje Cho

Ji Hwang Kim

Seunghoon Yeon

Sunkyoung Seo

Ohguk Kwon

Jongbo Shim

Jae Choon Kim

Jichul Kim

Namhoon Kim

Yun Seok Choi

Yonghoe Cho

Woohyun Park

Kyoung Soon Cho

Hyunsoo Chung

Chungsun Lee

Yonghwan Kwon

Seung-Kwan Ryu

Teak Hoon Lee

Sanguk Han

Yoonha Jung

Jisun Yang

Sungwoo Park

Tae Hong Min

Jeong-Woo Park

In-Young Lee

Kyol Park

Junyeong Heo

Sang Cheon Park

Sangcheon Park

Young Kun Jee

Chang-Seong Jeon

Pyoungwan Kim

Jin-Kwon Bae

Jae-hyun Phee

Moon Gi Cho

Uihyoung Lee

Minseung Yoon

Won Il Lee

Keumhee Ma

Keum-hee Ma

Heonwoo Kim

Hye-young Jang

Namseog Kim

Sungeun Pyo

Ha-Young Yim

A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

Semiconductor package

A semiconductor package includes an interposer substrate on a package substrate. The interposer substrate includes an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating the insulating layer between the upper surface and the lower surface to connect the upper pad and the lower pad. A semiconductor chip is disposed above the interposer substrate and connected to the upper pad, and a connection bump directly contacts a lower surface of the lower pad. The redistribution structure includes redistribution layers and redistribution vias connected to the redistribution layers, wherein each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and the lower pad directly contacts the plating seed layer.

A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

Semiconductor package and method of manufacturing the same

A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

Integrated circuit device and semiconductor package including the same

Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

Semiconductor package including an image sensor chip and a method of fabricating the same

A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.

A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

Semiconductor package and method of fabricating the same

An image sensor package comprises: an image sensor chip configured to convert light collected from an outside thereof into an electrical signal; a package substrate disposed under the image sensor chip the package substrate configured to process the electrical signal converted from the image sensor chip; a glass substrate disposed over the image sensor chip while being spaced apart from the image sensor chip; a seal pattern disposed between an upper surface of the package substrate and a lower surface of the glass substrate while surrounding the image sensor chip; and a protection pattern disposed on the package substrate outside the seal pattern, the protection pattern comprising a single-component material, wherein the seal pattern comprises a material different from the material of the protection pattern.

Image sensor package with underfill and image sensor module including the same

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Yongin-si, South Korea

Chajea Jo