Avago Technologies General IP (singapore) Pte. Ltd.

Emulex Corporation

Emulex Design & Manufacturing Corporation

Chaitanya Tumuluri

Parav Pandit

Kenny Meng-Hung Wu

Masoodur Rahman

Ravindra Sadanand Shenoy

Parag Bhide

Mukund T Chavan

Ashwin Kamath

Sujith Arramreddy

Anthony Hurson

Ganesh Boddapati

A rate limiter incorporated in a server connected to a network. The rate limiter is adapted to reduce congestion in the network in response to a congestion notification message. The server is adapted to send packets over the network. The rate limiter includes at least one of: a server rate limiter engine adapted to rate limit the packets in response to the server; a virtual machine rate limiter engine adapted to rate limit the packets in response to a virtual machine associated with the packets, the virtual machine hosted by the server; a flow rate limiter engine adapted to rate limit the packets in response to a flow associated with the packets; the flow being one of a plurality of flows transporting packets over the network; and a transmit engine adapted to rate limit the packets in response to a virtual pipe of the network for transmitting the packets.

Method and system for controlling traffic over a computer network

A method, network device and system for remote direct memory access (RDMA) over Converged Ethernet (RoCE) packet sequence acceleration are disclosed. The network device comprises one or more components for communicating with a host system. A network communication protocol, such as RoCE, is implemented by a combination of the one or more components and the host system.

RoCE packet sequence acceleration

When interfacing with a host, a networking device can handle a first data like Bulk Data Receive. The networking device can receive the first data and read a first queue entry from a receive queue in the host memory. In response to the read first queue entry, the networking device can write the first data to an unpinned memory in the host memory. The networking device can also handle a second data with a Receive Packet in Ring (RPIR) queue. The networking device can receive the second data and write the second data to a pinned memory in the host memory. The RPIR queue can be separate from or overlaid on the receive queue. High throughput and low-latency operation can be achieved. The use of a RPIR queue can facilitate the efficiency of resource utilization in the reception of data messages.

Low-latency packet receive method for networking devices

A method, network device and system for remote direct memory access (RDMA) over Converged Ethernet (RoCE) packet sequence acceleration are disclosed. The network device comprises one or more functionality components for communicating with a host system. The host system is configured for implementing a first set of functionalities of a network communication protocol, such as RoCE. The one or more functionality components are also operable to implement a second set of functionalities of the network communication protocol.

Disclosed herein are methods and apparatus for accelerating RoCE packet sequence transmission and reducing processing latency in received RoCE packets. Under the disclosed method, the RoCE protocol stack and RDMA verbs are implemented partially in the host software and partially in the adapter hardware, thereby providing a better balance between simplifying the adapter configuration and maximizing the host processing efficiency. Particularly, the adapter implemented with partial RoCE offload is able to perform a few major functionalities under the RoCE protocol, such as offloading a complete RoCE packet sequence for transmission, building individual packets out of the RoCE packet sequence and performing Invariant CRC calculation, insertion, validation and removal thereof.

A hardware switch for use with hypervisors and blade servers is disclosed. The hardware switch enables switching to occur between different guest OSs running in the same server, or between different servers in a multi-root IOV system, or between different guest OSs running in the same server in single-root IOV systems. Whether embedded in a host bus adapter (HBA), converged network adapter (CNA), network interface card (NIC) or other similar device, the hardware switch can provide fast switching with access to and sharing of at least one external network port such as a Fibre Channel (FC) port, 10 Gigabit Ethernet (10 GbE) port, FC over Ethernet (FCoE) port, or other similar port. The hardware switch can be utilized when no hypervisor is present or when one or more servers have hypervisors, because it allows for switching (e.g. Ethernet switching) between the OSs on a single hypervisor.

Growing community of inventors

Costa Mesa, CA, United States of America

Chaitanya Tumuluri