Intel Corporation

Chaitanya S Rajguru

Shekoufeh Qawami

Robert E Larsen

Lance W Dover

Kerry Dean Tedrow

Sandeep K Guliani

Mase J Taub

Sanjay S Talreja

Cesar Galindo

Kedar Mangrulkar

Jahanshir J Jayanifard

Waisum Wong

Various embodiments of the invention may provide one or more non-volatile storage entities, such as a register or a storage array, to store configuration information for a memory device. The specified configuration may then be enabled at the occurrence of a specified event, such as power-up and/or reset.

Non-volatile configuration data storage for a configurable memory

In one embodiment of the present invention, a method includes sensing a first burst length of data equal to half of a sense width of a plurality of sense amplifiers of a memory, and sensing a second burst length of data equal to the half of the sense width during a latency while sensing the first burst length of data.

Sensing word groups in a memory

A flash memory device includes a charge pump having a capacity that is preset to a particular value. The flash memory device includes a measuring circuit to measure the actual capacity of the charge pump and to reset the capacity of the charge pump to a value based on the measured capacity.

Flash memory program and erase operations

Briefly, in accordance with an embodiment of the invention, a method and system to retrieve information from a memory is provided. The method may include transferring information from the memory in response to at least two synchronous burst read requests using pipelining.

Method and system to retrieve information

A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first transistor gate voltage is substantially constant. The time delay circuit also includes a delay element. The output voltage of the first transistor biases the delay element.

Vcc independent time delay circuit

In one embodiment, the invention is an apparatus. The apparatus includes a column load component and a current mirror coupled in parallel with the column load component. The column load component is capable of being coupled to a FLASH cell and a sense amplifier.

Method and apparatus for low voltage sensing in flash memories

An integrated circuit arrangement for providing erase voltages to a flash EEPROM memory array including one charge pump for generating a first high voltage with substantial current which may be used for application to the source terminals of flash EEPROM memory cells during erase and to the gate terminals of flash EEPROM memory cells during programming, and another charge pump for generating a second lower voltage which may be used for application to the drain terminals of flash EEPROM memory cells during programming.

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Folsom, CA, United States of America

Chaitanya S Rajguru