Arizona State University

University of Texas System

Carnegie Mellon University

The University of Arizona

Chaitali Chakrabarti

Jae-sun Seo

Daniel W Bliss

Deepak Kadetotad

Joshua Mack

Anderson Sartor

Sumit Mandal

Anish Krishnakumar

Nirmal Kumbhare

Radu Marculescu

Ahmet Goksoy

Ali Akoglu

Sairam Arunachalam

Samet Egemen Arda

Umit Ogras

Hierarchical and lightweight imitation learning (IL) for power management of embedded systems-on-chip (SoCs), also referred to herein as HiLITE, is provided. Modern SoCs use dynamic power management (DPM) techniques to improve energy efficiency. However, existing techniques are unable to efficiently adapt the runtime decisions considering multiple objectives (e.g., energy and real-time requirements) simultaneously on heterogeneous platforms. To address this need, embodiments described herein propose HiLITE, a hierarchical IL framework that maximizes energy efficiency while satisfying soft real-time constraints on embedded SoCs. This approach first trains DPM policies using IL; then, it applies a regression policy at runtime to minimize deadline misses. HiLITE improves the energy-delay product by 40% on average, and reduces deadline misses by up to 76%, compared to state-of-the-art approaches. In addition, the trained policies not only achieve high accuracy, but also have negligible prediction time overhead and small memory footprint.

HiLITE: hierarchical and lightweight imitation learning for power management of embedded SoCs

Aspects disclosed in the detailed description include memory compression in a deep neural network (DNN). To support a DNN application, a fully connected weight matrix associated with a hidden layer(s) of the DNN is divided into a plurality of weight blocks to generate a weight block matrix with a first number of rows and a second number of columns. A selected number of weight blocks are randomly designated as active weight blocks in each of the first number of rows and updated exclusively during DNN training. The weight block matrix is compressed to generate a sparsified weight block matrix including exclusively active weight blocks. The second number of columns is compressed to reduce memory footprint and computation power, while the first number of rows is retained to maintain accuracy of the DNN, thus providing the DNN in an efficient hardware implementation without sacrificing accuracy of the DNN application.

Memory compression in a deep neural network

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Tempe, AZ, United States of America

Chaitali Chakrabarti