Altera Corporation

Chai Ling Chee

Eng Ling Ho

An apparatus to test a parametric structure utilizing a logical sensing technique is provided. The apparatus includes a device under test (DUT) and tester hardware. The DUT includes a parametric structure that receives a logic signal and transfers the logic signal through the parametric structure to a power pin that is coupled to the parametric structure. The DUT also includes a DFT circuitry that controls a pathway connecting the parametric structure and the power pin. The DFT circuitry gates the logic signal propagation from the parametric structure to the power pin. The tester hardware includes a channel to transfer or receive a logic signal and a power pathway to transfer power to the DUT. The tester hardware also includes a switch to multiplex the power pathway or the channel connections to the power pin.

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Jalan Van Praagh, Malaysia

Chai Ling Chee