Freescale Semiconductor,inc.

Freescale Semiconductors Inc.

Chai Ean E Gill

James D Whitfield

Rouying Zhan

Hongzhong Xu

Abhijat Goyal

An electrostatic discharge (ESD) protection device () coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (&#x2033;), each stage (&#x2033;) comprising first (T, T', T&#x2033;, etc.) and second transistors (T, T&#x2032;, T&#x2032;&#x2033; etc.) having a common collector (&#x2033;) and first (&#x2033;) and second (&#x2033;) emitters providing terminals (&#x2033;) of each clamp stage (. A first emitter () of the first stage () couples to the common terminal () and a second emitter (&#x2033;) of the last stage (&#x2032;) couples to the I/O terminals (). Zener diode triggers are not used. Integrated external ESD trigger resistors (&#x2033;) (e.g., of poly SC) are coupled between the base (&#x2033;) and emitter (&#x2033;) of each transistor (T, T&#x2032;, T&#x2033;; T, T&#x2032;, T&#x2033;). Different resistor values (e.g., &#x2dc;0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages () gives even higher trigger voltages. The ESD trigger resistances (&#x2033;) are desirably located outside the common collector-isolation wall (&#x2033;) surrounding the transistors (T, T&#x2032;, T&#x2033;; T, T&#x2032;, T&#x2033;).

Resistor triggered electrostatic discharge protection

An electrostatic discharge (ESD) protection device (), coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (), each stage () comprising an interior node () and first () and second terminal () nodes wherein the first terminal node () of the first clamp stage () is coupled to the common terminal () and the second terminal node () of the last clamp stages () is coupled to the I/O terminals (). A resistance-capacitance ladder () is provided in parallel with some of the clamp stages (), with a resistance (R, R, Retc.) coupled to each of the nodes (()) of one of the ESD clamp stages () by first terminals thereof and capacitors (C, C, etc.) are coupled between second terminals of the resistances (R, R, Retc.). The clamp stages () are desirably bi-directional and a diode (D) may bridge one or more of the clamp stages (e.g.,) to provide different clamp voltages for different polarity ESD events.

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Chandler, AZ, United States of America

Chai Ean E Gill