Taiwan Semiconductor Manufacturing Comp. Ltd.

Chai-Der Chang

Chi-Hung Liao

Cheng-Yu Chu

Sen-Fu Chen

Ching-Wen Cho

Szu-Hung Yang

Te-Fu Tseng

Kuo-Su Huang

Jen-Shiang Leu

Kuang-Peng Lin

Weng-Liang Fang

Tsu-Yu Chu

Yi-Tung Yen

Jow-Feng Lee

Pin-Hsiang Chin

Jyh-Ping Wang

Shing-Jzy Tay

Kuwi-Jen Chang

A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications. When directed towards forming patterned conductor layers, such as bond pads, the method optionally employs an inert plasma treatment of a patterned conductor layer followed by an aqueous ethanolamine treatment of the patterned conductor layer prior to a first plasma treatment of the patterned conductor layer.

Method for forming corrosion inhibited conductor layer

In accordance with the objectives of the invention a new method is provided for the definition and delineation of active regions in the surface of a semiconductor substrate. A layer of pad oxide is grown on the surface of the substrate, the layer of pad oxide is patterned and etched whereby the pad oxide remains in place over areas where the isolation regions are to be created. The underlying silicon substrate is in this manner exposed; the regions of the silicon substrate that are exposed are the regions of the substrate where active devices are to be created. The exposed surface of the substrate is cleaned; the openings in the layer of pad oxide are selectively filled with a deposition of epitaxial silicon. The created structure is heat treated to improve the interface between the patterned and etched layer of pad oxide and the deposited epitaxial silicon. The created pattern of pad oxide can now be used as regions of field isolation over the surface of the substrate.

Isolation method to replace STI for deep sub-micron VLSI process including epitaxial silicon

A method for making advanced guard rings in a stacked film on logic/merged DRAM circuits using a novel mask design is achieved. After forming a patterned amorphous silicon (a-Si) layer that has blanket portions over the logic region, a stacked film is deposited over the a-Si layer and extending over the edge and on the memory region. A first photoresist etch mask is used to pattern FET gate electrodes in the stacked film, and the etch mask includes a portion having a minimum width W over the edge of the a-Si layer to form a wide guard ring. This wide guard ring replaces a narrow guard ring that inadvertently forms during conventional processing and that is susceptible to peeling and particle contamination of the wafer. A second photoresist etch mask is used to pattern the a-Si layer to form FET gate electrodes over the logic region. The remaining process steps commonly practiced in the industry are carried out to complete the logic/merged DRAM circuit without the peeling and contamination that results from a narrow guard ring.

Method for making an advanced guard ring for stacked film using a novel mask design

A method for developing a semiconductor device low resistance electrical contact is described. In this process a gate oxide layer followed by a polysilicon layer is deposited on the semiconductor substrate in proximity to the device contact area. It is subsequently patterned with photoresist and etched to produce the desired gate structure. This is followed by a deposited layer of silicon dioxide or silicon nitride (SIN) which is appropriately patterned and etched to form gate isolation spacers. Then a nominal 300 &angst; layer of silicon nitride (SIN) is deposited followed by a layer of tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG). The contact area is defined by photolithography, and the passivation layers are etched either by a dry etch such as a RIE process, or a combination of a wet BOE process followed by a dry etch, to form the metal contact holes. Prior to sputtering the contact metal, the contact area is cleaned with a 30 second dip in a BOE solution, followed by a Hydrogen Peroxide (H,O,) dip. This H,O,cleaning step enables lower device contact resistance for the P&plus; contact areas.

Method to reduce device contact resistance using a hydrogen peroxide treatment

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Hsin-Chu, Taiwan

Chai-Der Chang