Synopsys, Inc.

Chaeryung Park

Henry Sheng

Mayank Shrivastava

Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in combination being different from the second library cell and second set of buffers in combination. The computer system selects among the candidate solutions at least in part in dependence upon sensitivity of the solution to load capacitance in the particular path, and stores the selected solution in the storage for subsequent use in further developing and fabricating an integrated circuit device.

Optimizing logic synthesis for environmental insensitivity

The number of scenarios analyzed for an electronic circuit is reduced to improve the processing time and resource requirements of electronic design automation processes. Each scenario is associated with a mode and a corner for the electronic circuit. Groups of scenarios corresponding to different corners for the same mode are identified. A winner scenario from each group is identified, for example, by selecting the dominant scenario from the group that covers the most number of violations in the group. The winner scenario is adjusted to account for violations of other scenarios of the group. The adjustment corresponding to a violation for a timing node from another scenario is performed by reducing the required time of the timing node in the winner scenario by a margin. The margin is determined based on timing information from the other scenario scaled to account for differences between the two scenarios.

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Saratoga, CA, United States of America

Chaeryung Park