Samsung Electronics Co., Ltd.

Konkuk University Industrial Cooperation Corp

Chae Seok Im

Shi Hwa Lee

Jae Don Lee

Seung Won Lee

Jung Park

Shi-hwa Lee

Min Kyu Jeong

Jeong Joon Yoo

Keun Soo Yim

Min Young Son

Woon Gee Kim

Hee Seok Kim

Dong-hoon Yoo

Young Sam Shin

Soo Jung Ryu

Jeong Wook Kim

Chang-Woo Baek

Seung Hyun Choi

Jung Keun Park

Jan Don Lee

A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information.

Apparatus and method managing power based on data

A memory overlay apparatus includes an internal memory that includes a dirty bit indicating a changed memory area, a memory management unit that controls an external memory to store only changed data so that only data actually being used by a task during overlay is stored and restored, and a direct memory access (DMA) management unit that confirms the dirty bit when the task is changed and that moves a data area of the task between the internal memory and the external memory.

Apparatus and method for memory overlay

Provided is an apparatus and method for managing power based on data. The apparatus may include a code segment searching unit configured to search for at least one code segment in which a power type is inserted, a block determining unit configured to determine at least one block based on the at least one found code segment, and a power mode control unit configured to control the at least one determined block to operate in a power mode corresponding to the power type.

Apparatus and method for managing power based on data

An apparatus and method for dynamically reconfiguring an Operating System (OS) for a manycore system are provided. The apparatus may include an application type determining unit to determine a type of an executed application, and an OS reconfiguring unit to activate only at least one function in an OS, based on the determined type of the application, and to reconfigure the OS.

Activating and deactivating Operating System (OS) function based on application type in manycore system

Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.

Apparatus and method for scratch pad memory management

An apparatus for performing partition scheduling in a manycore environment. The apparatus may perform partition scheduling based on a priority and in this instance, may perform partition scheduling to minimize the number of idle cores. The apparatus may include a partition queue to manage a partition scheduling event; a partition scheduler including a core map to store hardware information of each of the plurality of cores; and a partition manager to perform partition scheduling with respect to the plurality of cores in response to the partition scheduling event, using the hardware information.

Apparatus and method for partition scheduling for a processor with cores

Memory mapping in small units using a segment and subsegments is described, and thus it is possible to control a memory access even using a small amount of hardware, and it is possible to reduce costs incurred by hardware. Additionally, it is possible to prevent a memory from being destroyed due to a task error in the multi-processor system.

Apparatus and method for protecting memory in multi-processor system

Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor.

Computing system, method and computer-readable medium processing debug information in computing system

A synchronization scheduling apparatus and method in a real-time multi-core system are described. The synchronization scheduling apparatus may include a plurality of cores, each having at least one wait queue, a storage unit to store information regarding a first core receiving a wake-up signal in a previous cycle among the plurality of cores, and a scheduling processor to schedule tasks stored in the at least one wait queue, based on the information regarding the first core.

Synchronization scheduling apparatus and method in real-time multi-core system

Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated.

Hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization

A context switch method capable of promptly switching a context for a dynamically generated task and a dynamic link by converting a state of multiple register files, switching the context, and separately restoring and storing the context. That is, the context switch method includes: maintaining a multiple register files; establishing the multiple register to be in any one of a prefetch state, a current state, and a store state; converting a state of the multiple register files to be in any one of the prefetch state, the current state, and the store state when a context switch occurs; wherein, in the prefetch state, determining a memory address to read a next task context to be subsequently performed by the register file, in the current state, performing a task with the task context of the register file and in the store state, storing the register file in a memory.

Method and system for providing context switch using multiple register file

A method of transmitting data between processors, including: establishing and storing an encoding method for each area of virtual address space of a first processor in a predetermined storage device; determining an area of virtual address space corresponding to data to be transmitted to a second processor; and determining the encoding method corresponding to the determined area of the virtual address space with reference to the storage device and transmitting the data to the second processor by using the determined encoding method.

Method, system, and medium for providing interprocessor data communication

Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs.

Processor and interrupt handling method

A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.

Growing community of inventors

Suwon-si, South Korea

Chae Seok Im