Alcatel-lucent Canada Inc.

Alcatel Lucent

Chad William Kendall

Robert Elliott Robotham

Tom Edward Davis

Predrag Kostic

Robert Nesbitt

Joey Chow

Peter Irma August Barri

Bart Joseph Gerard Pauwels

Shay Nahum

Olivier Didier Duroyon

The invention relates to a telecommunication network having IP packet-supporting capabilities, which includes a load distribution processing function, either centralized or distributed, by means of which a load distribution function may be applied to sets of paths between network nodes or sets of links of network trunks. The load distribution processing function handles different load distribution functions. Each of the different load distribution functions is associated to a different network input unit involved in the load distribution for a set of paths between network nodes or a set of trunk links. The invention also relates to a method of load distribution in a telecommunication network as summarized above.

Method for distributing load over multiple shared resources in a communication network and network applying such a method

A packet processing device has an on-board match engine memory. Actions to be taken on a packet can be looked up in the match engine memory using a key comprising a match engine index and a protocol field from the packet. The match engine index is obtained from either a relatively small on-board parser memory or a larger context memory. The parser memory contains match engine indices for sparse protocols. Performance approaching that of hard-wired packet processors can be obtained. New protocols or changes in protocols can be accommodated by writing new values into the match engine, parser and context memories. The packet processing device can be provided in a pipelined architecture.

Configurable packet processor

An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory sections. Sequential parts of the software program are in sequential sections. The software program may have a common portion which is repeated in each of the memory sections. Arbiter logic may control which of the processing units accesses which of the memory sections in each memory access cycle.

Multiprocessor computing device having shared program memory

Apparatus for transmitting a data stream between cards connected by a midplane breaks the data stream into a plurality of channels. The apparatus comprises a serializer for each channel. Serialized data is transmitted across the midplane to a deserializer at the destination. Sequential cells are sent in different channels. Cell ordering is preserved by staggering the start of cell transmission in the channels. The invention permits data to be transmitted across a mid plane using a reduced number of data lines. The data stream on each card may be carried in a wide bus at a relatively low clock rate. Apparatus according to the invention may be used to transmit an OC-192 data stream across a pin-limited interface.

High speed sequenced multi-channel bus

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Vancouver, Canada

Chad William Kendall