Nvidia Corporation

Chad Plummer

Tezaswi Raja

Sachin Satish Idgunji

Brian Lawrence Smith

Hans Wolfgang Schulze

David Haley

Wen Yueh

Qi Lin

Siddharth Saxena

Tao Li

Ben Faulkner

Jun Gu

Vinayak Bhargav Srinath

Kartik Joshi

Darryl Moore

The disclosure provides a cooling solution that evaluates the thermal environment of a computer component based on transient thermal responses of the computer component. The transient thermal responses are generated by measuring the temperature rise of the computer component over a designated amount of time for multiple 'good' assemblies and multiple “bad” assemblies to determine a duration and allowable temperature rise needed to set a pass/fail criteria for different failure modes of cooling devices. A cooling device may not be operating as designed due to damage, needed maintenance, missing thermal interface material (TIM), improper installation, etc. From the transient thermal responses, a thermal problem, such as a malfunctioning fan, can be determined and a corrective action can be performed.

Thermal environment evaluation and compensation for computer components

Integrated circuits (ICs)&#x2014;depending on a current workload&#x2014;may exceed thermal cooling budgets. As a result, ICs often implement thermal sensors to measure temperatures at junctions or hot spots along the IC. Due to a distance between the thermal sensors and the various junctions, a thermal offset may be added to the temperature readings from the thermal sensors to more accurately estimate the temperature at the junctions. To account for different workload distributions&#x2014;e.g., asymmetric or symmetric&#x2014;the systems and methods described herein may dynamically adjust the thermal offsets. As a result, the efficiency of the IC may be increased as thermal settings for the IC may take into account the ability of the thermal cooling budget to effectively cool the IC under a current operating condition&#x2014;thereby reducing premature throttling back or shutting down of power to the IC.

Techniques for accurately determining the temperature at various locations of an operating integrated circuit

Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.

System frequency margin recovery via distributed critical path monitors (CPM)

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Bend, OR, United States of America

Chad Plummer