International Business Machines Corporation

Chad McIntyre

Reid T Copeland

Ali Ijaz Sheikh

Carlos D Cavanna

Jenna R Elliott

Fahad A Khan

Raymond C Kwong

Adam K D'Andrea

Sina Sadeghian Sadeghabad

Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.

Branch target buffer for emulation environments

Hybrid polymorphic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments

In an approach to reducing regression test duration, one or more computer processors receive a first code change. The one or more computer processors retrieve one or more historic code changes relevant to the first code change. The one or more computer processors determine whether one or more failed test cases are relevant to the one or more historic code changes, where the one or more relevant failed test cases and the one or more historic code changes are stored in a table of test history. In response to determining the one or more historic code changes are relevant to one or more failed test cases, the one or more computer processors retrieve the one or more relevant failed test cases from the table of test history.

Proactive and selective regression testing based on historic test results

Hybrid polymoprhic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments

Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed.

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Richmond Hill, Canada

Chad McIntyre