Unisys Corporation

Chad M Sonmore

Stephen Sutter

Kelvin S Vartti

David P Williams

James A Williams

Robert H Andrighetti

Conrad S Shimada

Jason D Lanfield

A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller coupled to the bus. The system bus implements one of a first and a second system bus protocols. The interface unit is compatible with the first system bus protocol in a first selectable mode and the second system bus protocol in a second selectable mode, and the controller is compatible with one of the system bus protocols. A mode register is coupled to the interface unit, and the interface unit selects the first mode responsive to a first value of the mode register and selects the second mode responsive to a second value of the mode register. A scan controller is coupled to the mode register for scanning a value into the mode register.

Dual mode capability for system bus

An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a 'page zero' instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, the IP issues one or more page zero requests using a background interface of the IP. In one embodiment, each request results in the initialization of a page of memory. While page zero requests are issued over the background interface, the IP may continue issuing other read and write requests to memory over a primary interface of the IP.

System and method for initializing memory within a data processing system

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Blaine, MN, United States of America

Chad M Sonmore