Intel Corporation

Chad Gutierrez

Guy M Therien

Russell Jerome Fenger

Premanand Sakarda

Rajshree Chabukswar

Deepak Samuel Kirubakaran

Monica Gupta

Jianwei Dai

Renji Thomas

Ramakrishnan Sivakumar

A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Hardware and software coordinated cost-aware low power state selection

Growing community of inventors

Santa Clara, CA, United States of America

Chad Gutierrez