International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Chad Edward Mitchell

Raymond Alan Richetta

Rick Allen Philpott

Joey Martin Poss

Jaydip Bhaumik

Vicki Lynn Pipal

Charles Joseph Masenas

Steven J Tanghe

Sharon Lynne Von Bruns

An apparatus for providing head amplitude characterization is disclosed. A DAC is used to apply known signals to a variable gain amplifier in the front end of a read channel. The signal is processed through the read channel and at the output of an ADC, the signal is read and used to determine the input channel amplitude. Knowing the amplitude of the two input signals, the ADC code spread and the two VGA gain codes, an equation is generated for determining the amplitude of a head.

Apparatus for providing head amplitude characterization

An apparatus for providing head amplitude characterization using gain loops is disclosed. A variable gain amplifier (VGA) receiving input signals and generates a VGA output signal. A digital-to-analog converter (DAC) circuit provides a desired input signal to the VGA and a gain control loop drives the VGA to gain lock the VGA to the provided desired input signal. An analog-to-digital converter (ADC) provides a digital output representing an ADC code spread in response to the VGA output. A controller drives the DAC to provide the desired input signal to the VGA and generates control signals for controlling the ADC, the controller further determines read head channel amplitude based upon the signal provided to the DAC, the ADC code spread received from the ADC and gain code provided by the gain control loops.

Apparatus for providing head amplitude characterization using gain loops

A method and structure for calibrating an analog to digital converter comprises an input signal; a driver receiving the input signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2 &minus;1 digital outputs; an encoding logic unit encoding the comparison result into n digital bits as an output signal; a calibration engine outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit receives the reference adjust signal, wherein the calibration engine receives n digital bits, and controls an operation of the driver or flash circuit based on the output signal.

Method and circuit for dynamic calibration of flash analog to digital converters

A system and method provides for calibrating a corner frequency of a tunable filter coupled to a read channel of a data storage system to a desired frequency. A signal having a frequency equal to the target corner frequency is generated. A gain of the signal is adjusted to a gain threshold. The gain of the signal is then increased from the gain threshold by a pre-established amount, such as by 3 dB. The corner frequency of the signal is shifted until the gain of the signal is substantially equal to the gain threshold, at which point the corner frequency of the tunable filter is calibrated to the desired frequency. The signal generated is a peak-detectable signal. The corner frequency of a tunable filter may be a low or high corner frequency appropriate for filtering a data signal or a servo signal. The corner frequency calibration circuitry may be implemented in-situ the read channel circuitry of a data storage system.

System and method for calibrating a corner frequency of a tunable filter employed in a read channel of a data storage system

An apparatus and method for calibrating a cutoff frequency of a tunable filter, such as a tunable filter coupled to a read channel of a data storage system is disclosed. A calibration circuit includes a variable gain amplifier (VGA), an envelope detector, and a tunable filter coupled therebetween. A calibration signal having a preestablished frequency representing a specified cutoff frequency associated with the tunable filter is applied to the VGA. The gain of the amplifier is adjusted until an amplitude of an output signal provided by the filter is substantially equal to a first predetermined amplitude. A cutoff frequency of the filter is then adjusted until an amplitude of an output signal provided by the filter is substantially equal to a second predetermined amplitude, at which time the desired cutoff frequency of the tunable filter is precisely established. A single cutoff frequency or the low and high cutoff freqencies of a range of cutoff frequencies may be calibrated. The envelope detector includes a number of analog comparators which are used to compare an output signal provided by the filter with predetermined voltage amplitudes provided by first and second reference voltage sources. A control circuit controls amplifier gain and adjusts the cutoff frequency of the filter. A cutoff frequency calibration circuit according to the present invention may be advantageously implemented in-situ a read channel of a disk drive system.

System and method for adjusting a cutoff frequency of a tunable filter employed in a read channel of a data storage system

A system and method are provided for calibrating a corner frequency of a tunable filter using an ADC code difference method. A method for calibrating a corner frequency of a tunable filter in a direct access storage device includes generating a signal having a frequency within a pass band of the tunable filter to be passed to the tunable filter. The gain of the signal is adjusted to a first threshold level. The corner frequency of the signal is shifted to a second threshold level, whereby the corner frequency of the tunable filter is calibrated at a desired frequency. A system for calibrating a corner frequency of a tunable filter in a direct access storage device includes calibrate control logic coupled to a tunable filter. A signal source generating a signal having a frequency within a pass band of the tunable filter to be passed to the tunable filter is coupled to the tunable filter by a variable gain amplifier. An analog-to-digital converter (ADC) is coupled to the tunable filter. The ADC produces a digitized signal in response to receiving the signal from the filter. The calibrate control logic adjusts a gain of the digitized signal to a first threshold level. The calibrate control logic shifts the corner frequency of the digitized signal to a second threshold level, whereby the corner frequency of the tunable filter is calibrated at a desired frequency. The first threshold level is set to a first ADC code and the second threshold level is set to a second ADC code. The second threshold level, second ADC code is set to the equivalent code of any given attenuation setting, for example, about 3 dB less than the first threshold level, first ADC code.

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Kasson, MN, United States of America

Chad Edward Mitchell