International Business Machines Corporation

Chad Andrew Marquart

Daniel Mark Dreps

Glen Arthur Wiedemeier

Yang You

Pier Andrea Francese

Erik English

Douglas J Malone

Dereje G Yilma

Venkat Harish Nammi

Jeffrey Kwabena Okyere

Christopher W Steffen

Andreas H A Arp

Jason Lee Frankel

Michael Wayne Harper

Franklin M Baez

Ching Lung Tong

Nathan Ross Blanchard

Vikram B Raj

Lily Jielu Zhang

Sudipto Chakraborty

Michael Sperling

Debjit Sinha

Vasant B Rao

Pawel Owczarczyk

Hemlata Gupta

Jin Hu

James Crugnale

Tyler Bohlke

Ze Zhang

A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module

Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.

High-speed deserializer with programmable and timing robust data slip function

Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers

A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

High-speed voltage clamp for unterminated transmission lines

A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.

Adjustable phase shifter

A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.

Phase rotator

Aspects of the invention include a driver arranged at a stand-alone receiver that is configured to receive a binary sequence from a pseudorandom binary sequence (PRBS) generator arranged at the receiver. The driver is configured to adjust the signal characteristics of the binary sequence to simulate channel loss at the receiver. The driver is further configured to output the adjusted binary sequence to a downstream data path of the receiver to enable the receiver to perform a self-test.

Built-in-self-test and characterization of a high speed serial link receiver

Embodiments are directed to continuous time linear equalization including a low frequency equalization circuit which maintains DC gain. A first all-pass filter is coupled to an integrated filter, the integrated filter having a low-pass filter and a second all-pass filter. A high-pass filter is coupled to the first all-pass filter and the integrated filter, a differential input terminal being coupled to the first all-pass filter, the integrated filter, and the high-pass filter, where a differential output terminal is coupled to the high-pass filter.

Continuous time linear equalization including a low frequency equalization circuit which maintains DC gain

An input/output (I/O) interface of a die is disclosed. The I/O interface of the die includes a first region of a backside of the die. The I/O interface further includes a second region of the backside surface of the die positioned along at least a portion of a perimeter of the first region. The second region provides power and ground connections to the first region.

Level shifting between interconnected chips having different voltage potentials

A method and apparatus are described to implement a bandpass filter in a current mode logic (CML) stage of a clock tree in an electronic system. The bandpass filter has a bandpass filter transfer function to attenuate frequencies lower than and higher than a carrier frequency. The bandpass filter uses adjustable active inductors and capacitive source degeneration. Adjustable resistors may be controlled to move a peak frequency of the bandpass filter transfer function to a higher or lower frequency. The adjustable active inductors and capacitive degeneration may consist of field effect transistors.

Jitter attenuation buffer structure

Aspects of the invention include a process for receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path, and determining that the first clock signal is arriving before the second clock signal by a difference quantity. Also, the process includes adding delay to the data path and the clock signal path according to the difference quantity.

Early mode protection for chip-to-chip synchronous interfaces

A method and apparatus in a receiver to determine if a high speed communication link is in an idle mode or in an active mode. Signals during the idle mode are of lower amplitude and lower frequency compared to amplitude and frequency in the active mode. A signal detector in the receiver determines if the high speed communication link has transitioned from idle mode to active mode and, if so, wakes up high power circuitry in the receiver to receive data.

Versatile signal detector circuit using common mode shift with all-pass characteristics

A computer program product for improved modeling of differential circuits is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to represent a configuration of a differential circuit on a defined space with representations of single-ended inputs and outputs disposed as differential input and output pairs along borders of the defined space, respectively, for each differential input and output pair, introduce an internal input or output differential node to feed from or to feed a corresponding differential input or output pair within the borders, respectively, with the internal input and output differential nodes being connectable and perform timing calculations with respect to input and output differential nodes.

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Austin, TX, United States of America

Chad Andrew Marquart