Impinj, Inc.

Synopsys, Inc.

Virage Logic Corporation

Chad A Lindhorst

Christopher J Diorio

Kambiz Rahimi

Theron Stanford

Harley K Heinrich

Scott A Cooper

Todd E Humes

Alberto Pesavento

Troy N Gilliland

Seth B Pollack

Terry D Hass

Gregory T Kavounas

John D Hyde

Shailendra Srinivas

Agustinus Sutandi

Miguel E Figueroa

Alex May

Shail Srinivas

Andrew Edward Horch

Paul F Dietrich

Yanjun Ma

Aanand Esterberg

Ali Aiouaz

Ernest Allen, Iii

RFID readers transmit a Quiet Technology (QT) command to RFID tags causing at least one of the tags to transition between a private profile and a public profile. When a tag is inventoried in the private profile, it replies to the reader with contents from its private memory. When a tag is inventoried in the public profile, it replies to the reader with contents from its public memory, where the contents of the public memory may be a subset and/or modified version of the private memory contents, or entirely different altogether. The tag's profile can be switched again by another QT command from the reader, or following a loss of power at the tag. An access password and/or a short-range mechanism may be employed to allow only authorized readers to transition tag profiles or interrogate the private memory contents of tags in the public profile.

RFID tags and readers employing QT command to switch tag profiles

Memory management units (MMUs) are disclosed. In one aspect, an MMU may have a first interface to a component. The first interface may receive one of a read of updated data from, and a write of updated data to, a virtual memory address. The virtual memory address may initially correspond to a first physical memory location in an only one time programmable (OTP) non-volatile memory (NVM). The MMU may have a remapping unit to remap a correspondence of the virtual memory address from the first physical memory location to a spare physical memory location. The MMU may also have a second interface to the OTP.NVM. The second interface may allow the updated data to be read from or written to the spare physical memory location of the OTP NVM. Methods performed by the MMUs, and methods and articles useful for manufacturing MMUs, are also disclosed.

Memory management unit (MMU) to make only one time programmable (OTP) memory appear multiple time programmable (MTP)

RFID tags, ICs for RFID tags, and methods are provided. In some embodiments, an RFID tag includes a memory with multiple sections, and a processing block. The processing block may map one of these sections, or another of these sections, for purposes of responding to a first command from an RFID reader. As such, an RFID tag can operate according to the data stored in the section mapped at the time. In some embodiments, a tag can even transition from mapping one of the sections to mapping another of the sections. This can amount to the tag exhibiting alternative behaviors, and permits hiding data on the tag.

RFID tag chips and tags with alternative behaviors and methods

Memory management units (MMUs) are disclosed. In one aspect, an MMU may have a first interface to a component. The first interface may receive one of a read of updated data from, and a write of updated data to, a virtual memory address. The virtual memory address may initially correspond to a first physical memory location in an only one time programmable (OTP) non-volatile memory (NVM). The MMU may have a remapping unit to remap a correspondence of the virtual memory address from the first physical memory location to a spare physical memory location. The MMU may also have a second interface to the OTP NVM. The second interface may allow the updated data to be read from or written to the spare physical memory location of the OTP NVM. Methods performed by the MMUs, and methods and articles useful for manufacturing MMUs, are also disclosed.

RFID tag semiconductor chip with memory management unit (MMU) to make only one time programmable (OTP) memory appear multiple times programmable (MTP)

Memory management unit (MMU) to make only one time programmable (OTP) memory appear multiple times programmable (MTP)

RFID tags and chips for RFID tags are capable of being inventoried in one or more early attempts. These tags are capable of then refraining from participating in one or more subsequent inventorying attempts. In some embodiments refraining is performed solely by the tag, while in others it is guided by the RFID reader. In some embodiments, an inventoried indicator in the tag becomes updated upon backscattering. The updated value is used by the tag to recognize a subsequent attempt, and thus refrain from participating in it. This permits the subsequent attempt to be used more intensively for inventorying the more elusive, harder-to-read tags, especially in more demanding scenarios.

RFID tag chips and tags refraining from participating in a subsequent inventorying attempt and methods

One Time Programmable (OTP) memory structures and methods for pretesting the support circuitry are provided. A group of dedicated test cells associated with one or more groups of regular OTP cells are used to test the support circuitry for the regular OTP cells. The dedicated cells are programmed and read. The read values are compared to the programmed values or expected values. As a result of the comparison, failing memories may be designated 'Not Usable', while regular OTP cells of passing memories can be programmed for their purpose resulting in elimination of wasted memories during test.

One time programmable memory test structures and methods

A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Apparatus for trimming high-resolution digital-to-analog converter

Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

Adaptive programming of memory circuit including writing data in cells of a memory circuit

Methods for adaptive programming of memory circuit including writing data in cells of a memory circuit

Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

Counteracting overtunneling in nonvolatile memory cells

Counteracting overtunneling in nonvolatile memory cells using charge extraction control

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Seattle, WA, United States of America

Chad A Lindhorst