Samsung Electronics Co., Ltd.

Cha-jea Jo

Tae-Je Cho

Un-Byoung Kang

Yun-seok Choi

Ji-hwang Kim

Yun-hyeok Im

Tae-je Cho

Hyeok-Man Kwon

Sang-Cheon Park

A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.

Method of fabricating a packaged integrated circuit with through-silicon via an inner substrate

A photonic integrated circuit is provided. The photonic integrated circuit includes a substrate having a through hole interconnecting a first surface and a second surface; a transmission wire passing through the through hole and including an optical transmission structure and an electrical transmission structure; and an optical-to-electrical converter connected to the optical transmission structure of the transmission wire on the first surface.

Photonic integrated circuit

A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.

Semiconductor package having stacked semiconductor chips

Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

Growing community of inventors

Incheon, South Korea

Cha-jea Jo