Industrial Technology Research Institute

Cha-Hsin Lin

Lurng-Shehng Lee

Tzu-Kun Ku

Ching-Chiun Wang

Zing-Way Pei

Shang-Chun Chen

Pei-Jer Tzeng

Shing-Chii Lu

Wen-Yi Hsieh

Yu-Chen Hsin

Pei-Ren Jeng

Chee-Wee Liu

Ming-Jinn Tsai

Erh-Hao Chen

Chung-Chih Wang

Wen-Miao Lo

Lurng-Sheng Lee

Maikap Siddheswar

A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars.

Semiconductor device and manufacturing method thereof

A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via.

Method for manufacturing through substrate via (TSV), structure and control method of TSV capacitance

A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit.

Semiconductor structure and manufacturing method thereof

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

TSV substrate structure and the stacked assembly thereof

A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes following steps. A mold is provided. The mold has a chamber and a plurality of protrusions in the chamber. A thermosetting material is injected into the chamber. The thermosetting material is cured. A parting step is performed to separate the cured thermosetting material from the mold, so as to form an interposer substrate. A plurality of blind holes corresponding to the protrusions is formed on the interposer substrate. A conductive material is filled into the blind holes to form a plurality of conductive pillars. A conductive pattern layer is formed on a surface of the interposer substrate. The conductive pattern layer is electrically connected with the conductive pillars.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a device layer and a least one conductive post. The substrate includes a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the substrate. The substrate includes a first side wall portion and a second side wall portion at the through hole. The first side wall portion is connected to the first surface and includes a plurality of first scallops. The second side wall portion is connected to the second surface and includes a non-scalloped surface. The device layer is disposed on the second surface, and the second side wall portion of the substrate further extends into the device layer along the non-scalloped surface. The conductive post is disposed in the through hole, wherein the conductive post is electrically connected to the device layer.

A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Semiconductor structure with conductive plug in an oxide layer

Method of fabricating oxide material layer with openings attached to device layers

A conductive bridging random access memory (CBRAM) device and a method of manufacturing the same are provided. The CBRAM device includes a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer. The second electrode layer is located on the solid electrolyte layer. The metal layer is located near the solid electrolyte layer. The dielectric layer is located between the solid electrolyte layer and the metal layer. Since the metal layer is disposed near the solid electrolyte layer in the CBRAM device, it can generate a positive electric field during an erase operation, so as to accelerate a break of mutually connected metal filaments.

Conductive bridging random access memory device and method of manufacturing the same

A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.

Bottom electrode of metal-insulator-metal capacitor

Electrolyte transistor including a gate structure, two sources/drains, an electrolyte layer and a buried conductive layer is provided. The gate structure including a gate dielectric layer and a gate is located above a substrate. The two sources/drains are separated from each other and located above the substrate on each side the gate structure. The electrolyte layer is located between and contacts the two sources/drains, and located between and contacts the gate structure and the substrate. The buried conductive layer is located between the electrolyte layer and the substrate. The electrolyte layer between the two sources/drains includes a channel. The conductivity of the electrolyte layer between the two sources/drains is changed by a redox reaction, so as to turn on or turn off the channel.

Electrolyte transistor

A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO) layers and at least one tetragonal structure material layer. The tetragonal structure material layer is disposed between two titanium oxide layers and each tetragonal structure material layer has the same or a different thickness. Leakage path can be cut off through the tetragonal material layer between the titanium oxide layers. In the meantime, the tetragonal structure material layer can induce the titanium oxide layers to transform into a high k rutile phase.

Metal-insulator-metal capacitor

A method of fabricating a solid state electrolytes memory device is provided. An insulator layer is formed on a substrate. A conductive layer is formed on the insulator layer. At least two openings partially overlapped and capable of communicating with each other are formed in the conductive layer, so that the conductive layer forms at least a pair of tip electrodes. Thereafter, solid state electrolytes are filled in the openings.

Solid state electrolyte memory device and method of fabricating the same

A method of fabricating a photodetector device includes preparing a silicon substrate, forming a patterned mesa on the silicon substrate, and forming a patterned conductive layer over the patterned mesa.

Silicon based photodetector

A non-volatile memory device and fabricating method thereof are provided. In the deposition to form a tunneling dielectric layer, a composite charge trapping layer and a block dielectric layer, an ingredient of a depositing material or the depositing material is adjusted to form a grading energy level structure, such that carriers are trapped or erased more easily in accordance with a variation in grading energy level. Therefore, the carriers are stored more effectively and the probability that the electric leakage occurs is reduced substantially.

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Tainan, Taiwan

Cha-Hsin Lin